• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.44-54
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• 2001

In this paper, a novel test method is proposed to detect the hard and soft fault in analog circuits. The proposed test method makes use of the offset voltage, which is one of the op-amps characteristics. During the test mode, CUT is modified to unit gain op-amps with feedback loop. When the input of the op-amp is grounded, a good circuit has a small offset voltage, but a faulty circuit has a large offset voltage. Faults in the op-amp which cause the offset voltage exceeding predefined range of tolerance can be detected. In the proposed method, no test vector is required to be applied. Therefore the test vector generation problem is eliminated and the test time and cost is reduced. In this note, the validity of the proposed test method has been verified through the example of the dual slope A/D converter. The HSPICE simulations results affirm that the presented method assures a high fault coverage.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.9
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• pp.275-284
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• 2016

The software used in the nuclear safety field has been ensured through the development, validation, safety analysis, and quality assurance activities throughout the entire process life cycle from the planning phase to the installation phase. However, this evaluation through the development and validation process needs a lot of time and money, and there are limitations to ensure that the quality is improved enough. Therefore, the effort to calculate the reliability of the software continues for a quantitative evaluation instead of a qualitative evaluation. In this paper, we propose a reliability evaluation method for the software to be used for a specific operation of the digital controller in a nuclear power plant. After injecting weighted faults in the internal space of a developed controller and calculating the ability to detect the injected faults using diagnostic software, we can evaluate the software reliability of a digital controller in a nuclear power plant.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.325-332
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• 2017

In this paper, a survey of test sequence generation methods for testing the conformance of a protocol implementation to its specification is presented. The best known methods proposed in the literature are called transition tour, distinguishing sequence, characterizing sequence, and unique input/output sequence. Also, several variants of the above methods are introduced. Applications of these methods to the finite state machine model are discussed. Then, comparative analysis of the methods is made in terms of test sequence length. Finally, conclusions are given as follows. The T-method produces the shortest test sequence, but it has the worst fault coverage. The W-method tends to produce excessively long test sequences even though its fault coverage is complete. The problem with the DS-method is that a distinguishing sequence may not exist. The UIO-method is more widely applicable, but it does not provide the same fault coverage as the DS-method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.11-20
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• 1998

Testability analysis computes controllabilities and observabilities of all lines of a circuit and then evaluates fault coverage. The values of controllability and observability as well as fault coverage produced by testability analysis are used for applications of testability analysis. ITEM was evaluated as a fault coverage tool. But the values of controllability and observability at all lines of circuits must be estimated as a performance measure of testability tools for another application such as partial scan. In this paper, partial scan method based on sensitivity analysis which estimates relative improvement of detectability of circuits after scanning a flip-flop is used for performance evaluation of ITEM. Performance of ITEM, with respect to testability values on each net, has been measured by comparing ITEM and STAFAN. Partial scan performance achieved by ITEM is very similar to that of STAFAN, but ITEM takes less CPU time. Therefore ITEM is very efficient for partial scan application because ITEM runs faster for very large circuits in which execution time is critical.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.1-10
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• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.100-105
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• 2003

In this paper, we propose the novel test method effectively to detect short and open faults in CMOS op-amp. The proposed method uses a sinusoidal signal with higher frequency than unit gain bandwidth. Since the proposed test method doesn't need complex algorithm to generate test pattern, the time of test pattern generation is short, and test cost is reduced because a single test pattern is able to detect all target faults. To verify the proposed method, CMOS two-stage operational amplifier with short and open faults is designed and the simulation results of HSPICE for the circuit have shown that the proposed test method can detect short and open faults in CMOS op-amp.

• Journal of Computing Science and Engineering
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• v.9 no.3
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• pp.142-154
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• 2015

Fault localization techniques help locate faults in source codes by exploiting collected test information and have shown promising results. To precisely locate faults, the techniques require a large number of test cases that sufficiently exercise the executable statements together with the label information of each test case as a failure or a success. However, during the process of software development, developers may not have high-coverage test cases to effectively locate faults. With the test case generation techniques, a large number of test cases without expected outputs can be automatically generated. Whereas the execution results for generated test cases need to be inspected by developers, which brings much manual effort and potentially hampers fault-localization effectiveness. To address this problem, this paper presents a method to select a few test cases from a number of test cases without expected outputs for result inspection, and in the meantime selected test cases can still support effective fault localization. The experimental results show that our approach can significantly reduce the number of test cases that need to be inspected by developers and the effectiveness of fault localization techniques is close to that of whole test cases.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.7
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• pp.994-1002
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• 2013

This study suggests a generalized availability and safety evaluation model to evaluate the influences to the system's fault tolerant capabilities depending on automatic fault detection function such as the automatic periodic testings. The conventional evaluation model of automatic fault detection function deals only with the self diagnostics, and supposes that the fault detection coverage of self diagnostics is always constant. But all of the fault detection methods could be degraded. For example, the periodic surveillance test has the potential human errors or test equipment errors, the self diagnostics has the potential degradation of built-in logics, and the automatic periodic testing has the potential degradation of automatic test facilities. The suggested evaluation models have incorporated the loss or erroneous behaviors of the automatic fault detection methods. The availability and the safety of each module of the safety grade platform have been evaluated as they were applied the automatic periodic test methodology and the fault tolerant evaluation models. The availability and safety of the safety grade platform were improved when applied the automatic periodic testing. Especially the fault tolerant capability of the processor module with a weak self-diagnostics and the process parameter input modules were dramatically improved compared to the conventional cases. In addition, as a result of the safety evaluation of the digital reactor protection system, the system safety of the digital parts was improved about 4 times compared to the conventional cases.

• Proceedings of the Korean Nuclear Society Conference
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• 2003.10a
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• pp.162.2-162.2
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• 2003