• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
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• pp.416-418
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• 1997

Stable power source and fast control response are important for the generator excitation system. To stabilize the control of excitation circuit the PI controller for excitation current has been used. But the response of the system with this conventional control technique is very poor, especially in transient response with a predictive current control, the response of the excitation system can be improved. In this study, it is verified by the PSIM simulation.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제51권6호
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• pp.313-320
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• 2002

In this paper, a new current controller with fast transient response is Proposed. The basic concept is to find the optimal control voltage for tracking the reference current with minimum time under the voltage limit constraint. The generalized solution of the minimum time current control in the systems are presented in this paper. With the generalized solution, the minimum time current controller can be easily applied to all the 3-phase balanced system. Through the simulation and the experiment, it is observed that the proposed controller has much less transient time than the conventional synchronous PI regulator.

• 조명전기설비학회논문지
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• 제21권5호
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• pp.82-89
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• 2007

여자제어 시스템의 AVR(Automatic Voltage Regulator) 장치는 발전기의 출력 전압을 일정하게 유지시키기 위하여, 여자기의 전압 또는 전류를 발전기 부하 전류 및 전압 변동에 따라 제어하는 역할을 수행한다. 이러한 AVR 장치의 응답성과 제어 특성은 발전기의 부하 변동 또는 과도 응답 상태에서의 출력 특성을 결정하게 된다. 본 논문에서는 고성능 전동기 제어 시스템에 널리 사용되고 있는 PWM 제어 시스템과 부하 변동에 강인하게 동작할 수 있는 과도 응답 보상기를 적용한 고성능 여자 시스템을 제안한다. 과도 응답 보상기는 발전기의 부하 전류 변동에 따라, 여자기의 제어신호를 PID 제어기의 출력에 더하여 빠른 속응성과 안정성을 가지도록 함으로써, 발전기의 출력 전압을 안정적으로 공급할 수 있도록 제어한다. 제안된 고성능 여자 시스템은 컴퓨터 시뮬레이션과 소형 발전기 시스템에 적용된 실험을 통하여 그 성능을 검증하였다.

• Nuclear Engineering and Technology
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• 제17권4호
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• pp.256-266
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• 1985

냉각재 유량상실 사고가 가압경수형 원자로인 고리 1호기에 대하여 해석되었다. 냉각재 유량 상실 사고는 그 심각도에 따라 다음과 같이 3가지로 분류된다. 즉, 일부 유량 상실사고, 완전 유량 상실 사고, 그리고 펌프 축 고착 사고이다. 사고 해석은 계통 과도 현상 및 평균 노심분석, DNBR 계산, 그리고 고온점 분석의 3단계로 수행된다. 원자로 계통과도 현상 코드인 KTRAN이 본 사고를 빠른 시간에 모사할 수 있도록 개발되었다. DNBR계산을 위해서는 열수력학 코드인 SCAN및 COBRA IV-I가 채택되었으며, 고온점 분석을 위해서는 연료봉 과도 현상 코드인 LTRAN이 쓰였다. 이러한 전산코드 시스템은 과도 현상 해석에 빨리 응답하여야 한다. 왜냐하면 사고가 발생한 후 수 초안에 심각한 상태에 이르기 때문이다. 불행히도 KTRAN코드에 의하여 이러한 목적은 충족되지 않았다. 그러나 다른 계통 해석 코드에 비하여 잔은 계산 시간에도 불구하고 KTRAN에 의한 계산 결과는 FSAR의 결과와 전반적으로 잘 일치함으로써 KTRAN코드가 사고 해석에 유용함이 밝혀졌다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1523-1535
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• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• Transactions on Electrical and Electronic Materials
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• 제17권3호
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• pp.172-177
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• 2016

Miller feedback compensation is introduced in a low dropout regulator (LDO) in order to obtain a capacitor-free regulator and improve the fast transient response. The conventional LDO has a limited bandwidth because of the large-size output capacitor and parasitic gate capacitance in the power MOSFET. In order to obtain a stable frequency response without the output capacitor, LDO is designed with resistor-capacitor (R-C) compensation and this is achieved with a connection between the gain-stage and the power MOS. An R-C compensator is suggested to provide a pole and zero to improve the stability. The proposed LDO is designed with the 0.35 μm CMOS process. Simulation testing shows that the phase margin in the Bode plot indicates a stable response, which is over 100^o. In the load regulation, the transient time is within 55 μs when the load current changes from 0.1 to 1 mA.

• Structural Engineering and Mechanics
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• 제31권2호
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• pp.211-223
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• 2009

Transient response analysis can be conducted either in the time domain, or via the frequency domain. Sometimes a frequency domain method (FDM) has advantages over a time domain method. A practical issue in the FDM is to find out an appropriate extended period, which may be affected by several factors, such as the excitation duration, the system damping, the artificial damping, the period of interest, etc. In this report, the extended period of the FDM based on the Duhamel's integral is investigated. This Duhamel's integral based FDM does not involve the unit impulse response function (UIRF) beyond the period of interest. Due to this fact, the ever-lasting UIRF can be simply set as zero beyond the period of interest to shorten the extended period. As a result, the preferred extended period is the summation of the period of interest and the excitation duration. This conclusion is validated by numerical examples. If the extended period is too short, then the front portion of the period of interest is more prone to errors than the rear portion, but the free vibration segment is free of the wraparound error.

• Journal of Power Electronics
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• 제16권6호
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• pp.2212-2220
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• 2016

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

• Advances in aircraft and spacecraft science
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• 제5권2호
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• pp.177-186
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• 2018

This paper deals with the idea to replace the usual high-level sine sweep test on shaker at system level, very severe, by a low level one completed by a transient test in the same configuration, in order to be more representative of the real environment, thus limiting over testing and improving the payload comfort. The problem of the transient test specification is first discussed. The proposed solution is to derive from LV/SC coupled analyses a shock response spectrum corresponding to two damping ratios. Then, the question of adequate shock synthesis is tackled. A new method with a given spectrum is considered for better potential and accuracy than the usual wavelets. A campaign on the Intespace bi-shaker devoted to system level showed its capability to perform the resulting test with one spectrum. First investigations to extend this approach to two spectra are in progress.

• ETRI Journal
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• 제42권5호
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.