• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Korean Journal of Materials Research
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• v.12 no.10
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• pp.820-824
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• 2002

It is of importance to know that the bonding strength and interfacial stress of SOI wafer pairs to meet with mechanical and thermal stresses during process. We fabricated Si/2000$\AA$-SiO$_2$ ∥ 2000$\AA$-SiO$_2$/Si SOI wafer pairs with electric furnace annealing, rapid thermal annealing (RTA), and fast linear annealing (FLA), respectively, by varying the annealing temperatures at a given annealing process. Bonding strength and interfacial stress were measured by a razor blade crack opening method and a laser curvature characterization method, respectively. All the annealing process induced the tensile thermal stresses. Electrical furnace annealing achieved the maximum bonding strength at $1000^{\circ}C$-2 hr anneal, while it produced constant thermal tensile stress by $1000^{\circ}C$. RTA showed very small bonding strength due to premating failure during annealing. FLA showed enough bonding strength at $500^{\circ}C$, however large thermal tensile stress were induced. We confirmed that premated wafer pairs should have appropriate compressive interfacial stress to compensate the thermal tensile stress during a given annealing process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3A
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• pp.284-289
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• 2002

In this paper, we propose the fast simulated annealing algorithm to decrease convergence rate in image segmentation using MRF. Simulated annealing algorithm has a good performance in noisy image or texture image, But there is a problem to have a long convergence rate. To fad a solution to this problem, we have labeled each pixel adaptively according to its intensity before simulated annealing. Then, we show the superiority of proposed method through experimental results.

• Journal of the Korean Magnetics Society
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• v.11 no.2
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• pp.78-83
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• 2001

The thermal characteristics of TMR devices by using Fast Linear Annealing method has been studied. A computer program that employs the finite differential method has been developed to simulate the temperature distribution of a diameter of 4" silicon wafer, which is subjected to radiation heat from the halogen lamp. We adopted the temperature of 350$\^{C}$, which is the highest temperature usually used in annealing for magnetic thin films. We changed moving velocity of the lamp from 0.05 mm/sec to 1 mm/sec. The moving velocity of halogen lamp has less effect on the local peak temperature of the sample only about 40$\^{C}$. Therefore, we may be able to anneal TMR devices in such short time of 1 minute and 40 seconds per one wafer, using the Fast Linear Annealing method.

• Korean Journal of Materials Research
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• v.14 no.5
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• pp.315-321
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• 2004

The void evolution in direct bonding process of $Si/Si_3$$N_4$ ∥ $SiO_2$/Si silicon wafer pairs has been investigated with an infrared camera. The voids that formed in the premating process grew in the conventional furnace annealing process at a temperature of $600^{\circ}C$. The voids are never shrunken even with the additional annealing process at the higher temperatures. We observed that the voids became smaller and disappeared with sequential scanning by our newly proposed fast linear annealing(FLA). FLA irradiates the focused line-shape halogen light on the surface while wafer moves from one edge to the other. We also propose the void shrinking mechanism in FLA with the finite differential method (FDM). Our results imply that we may eliminate the voids and enhance the yield for the direct bonding of wafer pairs by employing FLA.

• Electrical & Electronic Materials
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• v.9 no.3
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• pp.251-258
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• 1996

Sol-Gel derived ferroelectric Pb(Z $r_{0.52}$ $Ti_{0.48}$) $O_{3}$ thin films have been fabricated on Pt/Ti/ $SiO_{2}$/Si substrate. Two kinds of fast annealing methods, F-I (six times of intermediate and final annealing) and F-II(one final annealing after six times of intermediate annealing) were used for preparation of multi-coated PZT thin films. As the annealing temperature was increased, high capacitance could be obtained, for instance, 2700.angs.-thick PZT thin film annealed at 680.deg. C had a capacitance value of approximately 20nF at 1kHz. In addition, it is found that the dielectric constant is a function of the perovskite phase fraction. In case of F-I method, PZT thin film had a remanent polarization(Pr) of 8-15.mu.C/c $m^{2}$ and a coercive field( $E_{c}$) of 35-44kV/cm according to annealing temperature, whereas PZT film fabricated by F-II method had as high as 24-25.mu.C/c $m^{2}$ and 48-59kV/cm, respectively. As a result of measuring Curie temperature, PZT thin film had a range of 460-480.deg. C by F-I method and more or less higher range of 525-530.deg. C by F-II method, which implied that different microstructures could cause the different Curie temperature. Through I-V measurement, leakage current of PZT thin film fabricated by F-I and F-II methods was 64nA/c $m^{2}$ and 2.2.mu.A/c $m^{2}$ in the electric field of 100kV/cm, respectively.y.y.y.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.425-428
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• 2000

In this paper, we propose a new method based on SA(simulated annealing) with a fast algorithm for 3D image reconstructrion from the coded apereture images. The reconstructed images can be significantly improved by SA and to large computation cost of SA can be significantly reduced by the fast algorithm.

• ETRI Journal
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• v.32 no.6
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• pp.932-939
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• 2010

In this paper, a fast migration method is proposed. Our method executes local relocation on a model placement where an additional module is added to it for modification with a minimum number of displacements. This method is based on mean-field annealing (MFA), which produces a solution as reliable as a previously used method called simulated annealing. The proposed method requires substantially less time and hardware, and it is less sensitive to the initial and final temperatures. In addition, the solution runtime is mostly independent of the size and complexity of the input model placement. Our proposed MFA algorithm is optimized by enabling module rotation inside an energy function called permissible distances preservation energy. This, in turn, allows more options in moving the engaged modules. Finally, a three-phase cooling process governs the convergence of problem variables called neurons or spins.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• Progress in Superconductivity and Cryogenics
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• v.8 no.3
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• pp.5-8
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• 2006

The effect of annealing time in Metal Organic Deposition(MOD) method was investigated at reduced total pressure. As the total annealing pressure was reduced, the growth rate of YBCO films increased from 0.14nm/sec at atmospheric pressure to 4.2nm/sec at 1 Torr. For the total pres sure of 700, 500, 300, 100, and 1 Torr, the optimal annealing times of 60, 40, 20, 10, 2minutes were found in our experimental conditions. When the an nealing time was short, poor crystallinity or un-reacted phase was obtained. Also, the degradation of YBCO films occurred when exposed longer to the humid ambient at the high annealing temperature. The reduced pressure was found effective to in crease the growth rate and to control the pore size of the YBCO films in MOD method. A fast growth of MOD-YBCO films was realized with high critical current density over $1MA/cm^2$ using reduced pressure annealing. Large pores, usually observed at atmospheric pressure in MOD method, disappeared and also, the number of pores was reduced.