• Journal of Broadcast Engineering
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• v.21 no.5
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• pp.792-802
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• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.652-654
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• 2016

This paper shows the Design and implementation of sinusoidal BLDC motor drive logic using SVPWM method with FPGA. Sinusoidal BLDC motor driver logic consists of sine-wave PWM generator, dead-time and lead angle control logic. PWM generator logic is designed using SVPWM method for increase of 15.5% linear domain than general sine-wave PWM. This logic is verified and implemented using Spartan-6 FPGA Board. Test results show that THD(Total Harmonic Distortion) of motor-driving current is 19.2% and rotor position resolution is 1.6 degree.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.5
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• pp.55-63
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• 2007

This paper has investigated the susceptibility of an FPGA implementation of a block cipher against side channel analysis attacks. We have performed DPA attacks and DEMA attacks (in the nea. and far field) on an FPGA implementation of ARIA which has been implemented into two architectures of S-box. Although the number of needed traces for a successful attack is increased when compared with existing results on smart cards, we have shown that ARIA without countermeasures is indeed very susceptible to side channel analysis attacks regardless of an architecture of S-box.

• The Journal of the Acoustical Society of Korea
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• v.23 no.1
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• pp.17-23
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• 2004

The mobile radio channel can be simulated as a complex-valued random process with narrow-band spectrum. This paper describes a real-time implementation of that process using a INS320C6414 digital signal processor and XC2VP30 Virtex FPGA. The simulator presented here is not only a comprehensive model of the flat fading but also frequency selective fading mobile channel conditions. To replicate the statistical characteristics of the multipath fading environment with the minimum computational burden, multi-rate techniques are employed to resolve practical problems such as variable sampling rate. The simulator produces accurate and consistent results due to digital implementation. It is very flexible and simple to program for various field conditions in mobile communications with a graphical user interface.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.11
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• pp.1707-1712
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• 2013

In this paper, we implement a hardware for motor control based on FPGA + embedded processor using Zynq EPP which is All Programmable SoC in order to improve a structural problem of motion control based on such as DSP, MCU and FPGA previously. The implemented motor controller that is fused controller with advantage of FPGA and embedded processor. The signal processing part of high velocity motor control is performed by motor controller based on FPGA. A motion profile and kinematic calculation that are required algorithm process such as operation of a complicate decimal point has processed in an embedded processor based on dual core. As a result of a hardware implementation, it has an advantage that has can be realized an effect of distribution process in one chip. It has also an advantage that is able to organize as a multi-axis motor controller through adding the IP core of motor control implemented on FPGA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.4
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• pp.2363-2369
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• 2014

The DVR system supports multiple cameras and should be able to receive images at 30 frames per channel in real time. Thus, The system is using Full-HD-grade Multiplexer and Hardware compression codec. In this paper, Describing the design and implementation for the 4-channel Full-HD-grade PC-based DVR using FPGA and GPU inside CPU without Multiplexer and Hardware codec. The existing DVR system for Full-HD-grade has drawbacks to acquire images of about only 20 frames per channel in real time. The system to acquire images of multiple channel in real time was designed using FPGA. The software for the system was implemented using Intel Media SDK. At the result of performance evaluation, It was satisfied all for the required conditions. The practicality of the system was confirmed as implementation the system without using hardware compression.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.11
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• pp.1377-1383
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• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.369-370
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• 2013

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2013.05a
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• pp.381-382
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• 2013

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.8
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• pp.1142-1147
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• 2022

The edges of image should be detected first so that the objects in the image can be identified. An hardware-implemented edge detection algorithm outperforms its software version. Sobel operation is the most suitable algorithm for an hardware implementation of edge detection. And lots of works have been done to perform Sobel operations efficiently on FPGA-based hardware. This work proposes how to implement fast edge detection circuit on FPGA, which is based on the conventional circuit for edge detection using Sobel operator. The newly proposed circuit is suitable for processing images when the images are stored in memory devices and outperforms the conventional one with little additional FPGA resources. Both the conventional circuit and the proposed circuit were implemented on an FPGA. And the result showed that the proposed circuit almost doubles the performance in processing images and needs little additional FPGA resources.