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http://dx.doi.org/10.6109/jkiice.2019.23.11.1377

FPGA-based Implementation of Fast Histogram Equalization for Image Enhancement  

Ryu, Sang-Moon (Department of Information and Control Engineering, Kunsan National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.23, no.11, 2019 , pp. 1377-1383 More about this Journal
Abstract
Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.
Keywords
Image enhancement; Histogram equalization; FPGA; Parallel processing;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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