• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.6
• /
• pp.138-144
• /
• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.4
• /
• pp.888-894
• /
• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.355-362
• /
• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• The KIPS Transactions:PartA
• /
• v.14A no.7
• /
• pp.391-398
• /
• 2007

In this paper, we design a future mobile camera standard interface based on the MIPI CSI-2 and D-PHY specification. The proposed CSI-2 have the efficient multi-lane management layer, which the independent buffer on the each lane are merged into single buffer. This scheme can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. The proposed CSI-2 & D-PHY are verified under test bench. We make an experiment on CSI-2 & D-PHY with FPGA type test-bed and implement them onto a mobile handset. The proposed CSI-2 & D-PHY module are used as both the bridge type and the future camera processor IP for SoC.

• Journal of Korea Multimedia Society
• /
• v.10 no.7
• /
• pp.838-845
• /
• 2007

In this paper, we propose a modified cubic convolution scaler for the enlargement or reduction of digital images. The proposed method has less computational complexity than the cubic convolution method. In order to reduce the computational complexity, we use the linear function of the cubic convolution and the difference value of adjacent pixels for selecting interpolation methods. We employ adders and barrel shifts to calculate weights of the proposed method. The proposed method is compared with the conventional one for the computational complexity and the image quality. It has been designed and verified by HDL(Hardware Description Language), and synthesized using Xilinx Virtex FPGA.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.6 no.8
• /
• pp.1283-1291
• /
• 2002

In this paper, the PLL driven by the DDFS is designed on the schematic using the Q-logic cell based library and is implemented using FPGA QL32 x16B. The measurement results of the frequency synthesizer switching speed were agreement with a register. The simulated results show that the clock delay was generated after eleven clock and if input is random, It has influence on output DA converter has to be very extensive. Therefore, the DDFS used noise shaper to drive PLL by regular interval for input state. Also the bandwidth of DA converter very extensive, the simulation shows that the variation of small input control word is better than the switching speed of PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.401-403
• /
• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1C
• /
• pp.35-44
• /
• 2004

In this paper, we design an efficient VLSI architecture of entropy coding algorithm in JPEG2000. Entropy coder is a context-based binary arithmetic encoder, and composed of a Context Extractor(CE) and an Arithmetic Coder(AC). We speed-up CE by skipping no-operation bits in coding passes, and AC is to be performed based on MQ coder. Because of using Qe value associated with each allowed context and probability estimation, MQ coder is a multiplication free coder that reduces computation loads and makes simple the structure of arithmetic coder. We have developed and synthesized the VHDL models of CE and AC pairs using Xilinx FPGA technology. The proposed architecture operates up to 30MHz.

• Journal of the Institute of Electronics Engineers of Korea TE
• /
• v.37 no.3
• /
• pp.37-44
• /
• 2000

In this paper, an efficient hardware architecture of Lempel-Ziv compressor for real time data compression is proposed. The accumulated shift operations in the Lempel-Ziv algorithm are the major problem, because many shift operations are needed to prepare a dictionary buffer and matching symbols. A new efficient architecture for the fast processing of Lempel-Ziv algorithm is presented in this paper. In this architecture, the optimization technique for dictionary size, a new comparing method of multi symbol and a rotational FIFO structure are used to control shift operations easily. For the functional verification, this architecture was modeled by C programming language, and its operation was verified by running on commercial DSP processor. Also, the design of overall architecture in VHDL was synthesized on commercial FPGA chip. The result of critical path analysis shows that this architecture runs well at the input bit rate of 256kbps with 33MHz clock frequency.

• The Journal of the Korea Contents Association
• /
• v.16 no.3
• /
• pp.91-101
• /
• 2016

This paper presents the design of new parallel BCH decoder for MLC NAND flash memory. The proposed decoder supports the multi-byte parallel operations to enhance its throughput. In addition, it employs a LFSR-based parallel syndrome generator for compact hardware design. The proposed BCH decoder is synthesized with hardware description language, VHDL and it is verified using Xilinx FPGA board. From the simulation results, the proposed BCH decoder enhances the throughput by 2.4 times than its predecessor employing byte-wise parallel operation. Compared to the other counterpart employing a GFM-based parallel syndrome generator, the proposed BCH decoder requires the same number of cycles to complete the given works but the circuit size is reduced to less than one-third.