• Title/Summary/Keyword: FOWLP(Fan-out wafer level packaging)

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Numerical Analysis of Warpage and Reliability of Fan-out Wafer Level Package (수치해석을 이용한 팬 아웃 웨이퍼 레벨 패키지의 휨 경향 및 신뢰성 연구)

  • Lee, Mi Kyoung;Jeoung, Jin Wook;Ock, Jin Young;Choa, Sung-Hoon
    • Journal of the Microelectronics and Packaging Society
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    • v.21 no.1
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    • pp.31-39
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    • 2014
  • For mobile application, semiconductor packages are increasingly moving toward high density, miniaturization, lighter and multi-functions. Typical wafer level packages (WLP) is fan-in design, it can not meet high I/O requirement. The fan-out wafer level packages (FOWLPs) with reconfiguration technology have recently emerged as a new WLP technology. In FOWLP, warpage is one of the most critical issues since the thickness of FOWLP is thinner than traditional IC package and warpage of WLP is much larger than the die level package. Warpage affects the throughput and yield of the next manufacturing process as well as wafer handling and fabrication processability. In this study, we investigated the characteristics of warpage and main parameters which affect the warpage deformation of FOWLP using the finite element numerical simulation. In order to minimize the warpage, the characteristics of warpage for various epoxy mold compounds (EMCs) and carrier materials are investigated, and DOE optimization is also performed. In particular, warpage after EMC molding and after carrier detachment process were analyzed respectively. The simulation results indicate that the most influential factor on warpage is CTE of EMC after molding process. EMC material of low CTE and high Tg (glass transition temperature) will reduce the warpage. For carrier material, Alloy42 shows the lowest warpage. Therefore, considering the cost, oxidation and thermal conductivity, Alloy42 or SUS304 is recommend for a carrier material.

Plasma Application Technology of FOWLP (Fan-out Wafer Level Packaging) Process (FOWLP(Fan-out Wafer Level Packaging) 공정의 플라즈마 응용 기술)

  • Se Yong Park;Seong Eui Lee;Hee Chul Lee;Sung Yong Kim;Nam Sun Park;Kyoung Min Kim
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.1
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    • pp.42-48
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    • 2023
  • Recently, there has been an increasing demand for performance improvement and miniaturization in response to the growing variety of signals and power demands in many industries such as mobile, IoT, and automotive. As a result, there is a high demand for high-performance chips and advanced packaging technologies that can package such chips. In this context, the FOWLP process technology is a suitable technology, and this paper discusses the plasma application technologies that are being used and studied to improve the shortcomings of this process. The paper is divided into four parts, with an introduction and case studies for each of the plasma application technologies used in each part.

Heterogeneous Device Packaging Technology for the Internet of Things Applications (IoT 적용을 위한 다종 소자 전자패키징 기술)

  • Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.23 no.3
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    • pp.1-6
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    • 2016
  • The Internet of Things (IoT) is a new technology paradigm demanding one packaged system of various semiconductor and MEMS devices. Therefore, the development of electronic packaging technology with very high connectivity is essential for successful IoT applications. This paper discusses both fan-out wafer level packaging (FOWLP) and 3D stacking technologies to achieve the integrattion of heterogeneous devices for IoT. FOWLP has great advantages of high I/O density, high integration, and design flexibility, but ultra-fine pitch redistribution layer (RDL) and molding processes still remain as main challenges to resolve. 3D stacking is an emerging technology solving conventional packaging limits such as size, performance, cost, and scalability. Among various 3D stacking sequences wafer level via after bonding method will provide the highest connectivity with low cost. In addition substrates with ultra-thin thickness, ultra-fine pitch line/space, and low cost are required to improve system performance. The key substrate technologies are embedded trace, passive, and active substrates or ultra-thin coreless substrates.

Study of Organic-inorganic Hybrid Dielectric for the use of Redistribution Layers in Fan-out Wafer Level Packaging (팬 아웃 웨이퍼 레벨 패키징 재배선 적용을 위한 유무기 하이브리드 유전체 연구)

  • Song, Changmin;Kim, Sarah Eunkyung
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.4
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    • pp.53-58
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    • 2018
  • Since the scaling-down of IC devices has been reached to their physical limitations, several innovative packaging technologies such as 3D packaging, embedded packaging, and fan-out wafer level packaging (FOWLP) are actively studied. In this study the fabrication of organic-inorganic dielectric material was evaluated for the use of multi-structured redistribution layers (RDL) in FOWLP. Compared to current organic dielectrics such as PI or PBO an organic-inorganic hybrid dielectric called polysilsesquioxane (PSSQ) can improve mechanical, thermal, and electrical stabilities. polysilsesquioxane has also an excellent advantage of simultaneous curing and patterning through UV exposure. The polysilsesquioxane samples were fabricated by spin-coating on 6-inch Si wafer followed by pre-baking and UV exposure. With the 10 minutes of UV exposure polysilsesquioxane was fully cured and showed $2{\mu}m$ line-pattern formation. And the dielectric constant of cured polysilsesquioxane dielectrics was ranged from 2.0 to 2.4. It has been demonstrated that polysilsesquioxane dielectric can be patterned and cured by UV exposure alone without a high temperature curing process.

Effects of O2 Plasma Pre-treatment and Post-annealing Conditions on the Interfacial Adhesion Between Ti Thin Film and WPR Dielectric (O2 플라즈마 전처리 및 후속 열처리 조건이 Ti 박막과 WPR 절연층 사이의 계면 접착력에 미치는 영향)

  • Kim, Gahui;Lee, Jina;Park, Se-hoon;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.27 no.1
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    • pp.37-43
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    • 2020
  • The effects of O2 plasma pre-treatment and post-annealing conditions on the interfacial adhesion of Ti thin film and WPR dielectric were investigated using 90° peel test for fan-out wafer level packaging (FOWLP) redistribution layer (RDL) applications. Peel strength between Ti film and WPR dielectric decreased from 8.9±1.3 g/mm to 2.7±0.9 g/mm for variation of O2 plasma pre-treatment time from 30s to 300s, which is closely related to C-O-C or C=O bonds breakage at the WPR dielectric surface due to excessive plasma pre-treatment conditions. During post-annealing at 150℃, the peel strength abruptly decreased from 0 h to 24 h, and then maintained constant until 100 h, which is also mainly due to the damage of WPR dielectric which is weak to high temperature. Therefore, the optimum plasma pre-treatment conditions on the surface of dielectric is essential to interfacial reliability of FOWLP RDL.

A Study of Warpage Analysis According to Influence Factors in FOWLP Structure (FOWLP 구조의 영향 인자에 따른 휨 현상 해석 연구)

  • Jung, Cheong-Ha;Seo, Won;Kim, Gu-Sung
    • Journal of the Semiconductor & Display Technology
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    • v.17 no.4
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    • pp.42-45
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    • 2018
  • As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.

Analysis of Warpage of Fan-out Wafer Level Package According to Molding Process Thickness (몰드 두께에 의한 팬 아웃 웨이퍼 레벨 패키지의 Warpage 분석)

  • Seung Jun Moon;Jae Kyung Kim;Euy Sik Jeon
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.4
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    • pp.124-130
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    • 2023
  • Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

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Comparison of Quantitative Interfacial Adhesion Energy Measurement Method between Copper RDL and WPR Dielectric Interface for FOWLP Applications (FOWLP 적용을 위한 Cu 재배선과 WPR 절연층 계면의 정량적 계면접착에너지 측정방법 비교 평가)

  • Kim, Gahui;Lee, Jina;Park, Se-hoon;Kang, Sumin;Kim, Taek-Soo;Park, Young-Bae
    • Journal of the Microelectronics and Packaging Society
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    • v.25 no.2
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    • pp.41-48
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    • 2018
  • The quantitative interfacial adhesion energy measurement method of copper redistribution layer and WPR dielectric interface were investigated using $90^{\circ}$ peel test, 4-point bending test, double cantilever beam (DCB) measurement for FOWLP Applications. Measured interfacial adhesion energy values of all three methods were higher than $5J/m^2$, which is considered as a minimum criterion for reliable Cu/low-k integration with CMP processes without delamination. Measured energy values increase with increasing phase angle, that is, in order of DCB, 4-point bending test, and $90^{\circ}$ peel test due to increasing roughness-related shielding and plastic energy dissipation effects, which match well interfacial fracture mechanics theory. Considering adhesion specimen preparation process, phase angle, measurement accuracy and bonding energy levels, both DCB and 4-point bending test methods are recommended for quantitative adhesion energy measurement of RDL interface depending on the real application situations.

Effects of Dielectric Curing Temperature and T/H Treatment on the Interfacial Adhesion Energies of Ti/PBO for Cu RDL Applications of FOWLP (FOWLP Cu 재배선 적용을 위한 절연층 경화 온도 및 고온/고습 처리가 Ti/PBO 계면접착에너지에 미치는 영향)

  • Kirak Son;Gahui Kim;Young-Bae Park
    • Journal of the Microelectronics and Packaging Society
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    • v.30 no.2
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    • pp.52-59
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    • 2023
  • The effects of dielectric curing temperature and temperature/humidity treatment conditions on the interfacial adhesion energies between Ti diffusion barrier/polybenzoxazole (PBO) dielectric layers were systematically investigated for Cu redistribution layer applications of fan-out wafer level package. The initial interfacial adhesion energies were 16.63, 25.95, 16.58 J/m2 for PBO curing temperatures at 175, 200, and 225 ℃, respectively. X-ray photoelectron spectroscopy analysis showed that there exists a good correlation between the interfacial adhesion energy and the C-O peak area fractions at PBO delaminated surfaces. And the interfacial adhesion energies of samples cured at 200 ℃ decreased to 3.99 J/m2 after 500 h at 85 ℃/85 % relative humidity, possibly due to the weak boundary layer formation inside PBO near Ti/PBO interface.