• Title/Summary/Keyword: FFT signal processing

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Airborne Pulsed Doppler Radar Development (비행체 탑재 펄스 도플러 레이다 시험모델 개발)

  • Kwag, Young-Kil;Choi, Min-Su;Bae, Jae-Hoon;Jeon, In-Pyung;Yang, Ju-Yoel
    • Journal of Advanced Navigation Technology
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    • v.10 no.2
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    • pp.173-180
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    • 2006
  • An airborne radar is an essential aviation electronic system of the aircraft to perform various missions in all weather environments. This paper presents the design, development, and test results of the multi-mode pulsed Doppler radar system test model for helicopter-borne flight test. This radar system consists of 4 LRU units, which include ANTU(Antenna Unit), TRU(Tx Rx Unit), RSDU(Radar Signal & Data Processing Unit) and DISU(Display Unit). The developed technologies include the TACCAR processor, planar array antenna, TWTA transmitter, coherent I/Q detector, digital pulse compression, DSP based Doppler FFT filtering, adaptive CFAR, IMU, and tracking capability. The design performance of the developed radar system is verified through various helicopter-borne field tests including MTD (Moving Target Detector) capability for the Doppler compensation due to the moving platform motion.

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Design of 64-point $R^{2}SDF$ pipeline FFT processor in OFDM (OFDM을 위한 64점 $R^{2}SDF$ 파이프라인 FFT 프로세서 설계)

  • 이상한;이태욱;이종화;조상복
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1221-1224
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    • 2003
  • A 64-point R2$^2$ SDF pipeline FFT processor using a new efficient computation sharing multiplier was designed. Computation sharing multiplication specifically targets computation re-use in multiplication of coefficient vector by scalar and is effectively used in DSP(Digital Signal Processing). To reduce the number of multipliers in FFT, we used the proposed computation sharing multiplier. The 64-point pipeline FFT processor was implemented by VHDL and synthesized using Max+PLUSII of Altera. The simulation result shows that the proposed computation sharing multiplier can be reduced to about 17.8% logic cells compared with a conventional multiplier. This processor can operate at 33MHz and calculate a 64-point pipeline FFT in 1.94 $mutextrm{s}$.

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Implementation of Low Complexity FFT, ADC and DAC Blocks of an OFDM Transmitter Receiver Using Verilog

  • Joshi, Alok;Gupta, Dewansh Aditya;Jaipuriyar, Pravriti
    • Journal of Information Processing Systems
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    • v.15 no.3
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    • pp.670-681
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    • 2019
  • Orthogonal frequency division multiplexing (OFDM) is a system which is used to encode data using multiple carriers instead of the traditional single carrier system. This method improves the spectral efficiency (optimum use of bandwidth). It also lessens the effect of fading and intersymbol interference (ISI). In 1995, digital audio broadcast (DAB) adopted OFDM as the first standard using OFDM. Later in 1997, it was adopted for digital video broadcast (DVB). Currently, it has been adopted for WiMAX and LTE standards. In this project, a Verilog design is employed to implement an OFDM transmitter (DAC block) and receiver (FFT and ADC block). Generally, OFDM uses FFT and IFFT for modulation and demodulation. In this paper, 16-point FFT decimation-in-frequency (DIF) with the radix-2 algorithm and direct summation method have been analyzed. ADC and DAC in OFDM are used for conversion of the signal from analog to digital or vice-versa has also been analyzed. All the designs are simulated using Verilog on ModelSim simulator. The result generated from the FFT block after Verilog simulation has also been verified with MATLAB.

FFT에 기반한 병렬 디지털 신호처리시스템의 성능분석

  • 박준석;전창호;박성주;이동호;오원천;한기택
    • The Journal of the Acoustical Society of Korea
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    • v.18 no.1
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    • pp.3-9
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    • 1999
  • This paper concerns performance of a parallel digital signal processing system. The performance of the system is analyzed in terms of CPU cycles required for 1024-point FFT computation. The number of cycles is estimated in three different approaches; FFT algorithm-based, assembly level source code-based, and probability-based. The results of analysis indicate that on a bus-based system the best performance for FFT is achieved with a single board. Because in some applications like FFT, where frequent data exchanges among processors occur, the number of communication cycles increases as the number of boards. It is observed that inter-board communication degrades overall system performance for the FFT computation. Also shown is that linear increase in performance can be obtained if multiple buses are employed.

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Improving TDOA Measurement Accuracy for Software GPS Receiver (소프트웨어 GPS 수신기를 위한 의사거리 정밀도 향상 기법)

  • Hong, Jin-Seok;Kim, Hwi;Ji, Kyu-In
    • 제어로봇시스템학회:학술대회논문집
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    • 2000.10a
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    • pp.97-97
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    • 2000
  • In this paper, a signal processing algorithm for software GPS receiver is proposed. The signal processor takes snapshot of the sampled If signal from the RF section of the GPS receiver. All the processing for code and carrier tracking and correlation are implemented using the digital signal processing techniques. In order to achieve fast code acquisition, correlation of the incoming GPS signal is performed using the FFT method, After code acquisition, to reduce the Doppler shift effect and increase the accuracy, the interpolation or the tracking are performed. The performance of the proposed processing algorithm is first evaluated using matlab/simulink. A signal acquisition board for sampling and logging GPS IF signal form the Mitel GPS RF chip set is constructed. In order to analyze the performance of the designed algorithm the experiments are performed and the results are analyzed.

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Design of Low-complexity FFT Processor for Multi-mode Radar Signal Processing (멀티모드 레이다 신호처리를 위한 저복잡도 FFT 프로세서 설계)

  • Park, Yerim;Jung, Yongchul;Jung, Yunho
    • Journal of Advanced Navigation Technology
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    • v.24 no.2
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    • pp.85-91
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    • 2020
  • Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

FFT based Monitoring System for Combustion Vibration Data Processing of Gas Turbine (가스터빈 연소진동 데이터 처리를 위한 FFT 기반의 모니터링 시스템)

  • Lee, Sang-Hyeok;Kang, Feel-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2327-2334
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    • 2007
  • This paper presents a method for improvement of communication speed and reduction of data storage space in gas turbine monitoring system to acquire, save, and display combustion vibration data. The proposed method implements FFT from sampled raw data. The FFT result data are encoded to be transferred to monitoring PC for storage. By this way, it can reduce data storage space. To display the received data, it needs inverse FFT to reconstruct original signal. To verify the validity and efficiency of the proposed scheme, computer-aided simulation are carried out. It includes the analyzed results the relationship between FFT's order and Gibb's Phenomenon. Finally, high-performance of the proposed method is proved by combustion experiment results using a prototype gas turbine.

A Study on On-Line Quality Monitoring Using Arc Light in Gas Metal Arc Welding (GMAW에서 아크 빛을 이용한 실시간 용접품질 모니터링에 관한 연구)

  • 조택동;양상민
    • Journal of Welding and Joining
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    • v.18 no.4
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    • pp.82-86
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    • 2000
  • Gas metal arc welding(GMAW) is regarded as one of the best candidate for welding automation in industrial joining application. It is important to monitor the weld quality for the high performance weld automation. In GMAW, weld quality is closely related to arc stability especially. In this paper, arc light signal is measured and spectrum analyzed to the detect the variation of the weld quality. The FFT of the signal showed that the amplitude variance of FFT power spectrum was very large in poor weld process such as the decrease of weld bead width and height. The results show that it is possible to detect the weld defect position in weld process.

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Monitoring of Laser Material Processing Using Photodiodes (광 센서를 이용한 레이저 가공공정의 모니터링)

  • Park, Young-Hwan
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.10 no.3
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    • pp.515-520
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    • 2009
  • In this paper, the monitoring system was developed measuring the light signal emitted from the plasma in aluminum laser welding. Spectrum of plasma was measured using a spectrometer, and the photodiode was selected based on the spectrum analysis. The sensor signals for various welding conditions could be obtained, the characteristic of signal was closely related to the intensity and stability of plasma through mean value of signal and FFT analysis. The reason of signal fluctuation was behavior of plasma and keyhole and it was also connected with the surface bead shape of weld.

A New FFT Technique for the Analysis of Contact Pressure and Subsurface Stress in a Semi-Infinite Solid

  • Cho, Yong-Joo;Koo, Young-Pil;Kim, Tae-Wan
    • Journal of Mechanical Science and Technology
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    • v.14 no.3
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    • pp.331-337
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    • 2000
  • A numerical procedure for contact analysis and calculating subsurface stress was developed. The procedure takes the advantage of signal processing technique in frequency domain to achieve shorter computing time. Boussinesq's equation was adopted as a response function in contact analysis. The validity of this procedure was proved by comparing the numerical results with the exact solutions. The fastness of this procedure was also compared with other algorithm.

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