• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.8 no.4
• /
• pp.89-95
• /
• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Journal of IKEEE
• /
• v.25 no.4
• /
• pp.697-702
• /
• 2021

Fast Fourier Transform (FFT) is a major signal processing block being widely used. For long-point FFT processing, usually more than 1024 points, its low-complexity implementation becomes very important while retaining high SQNR (Signal-to-Quantization Noise Ratio). In this paper, we present a low-complexity FFT algorithm with a simple dynamic scaling scheme. For the 2048-point pipelined FFT processing, we can reduce the number of general multipliers by half compared to the well-known radix-2 algorithm. Also, the table size for twiddle factors is reduced to 35% and 53% compared to the radix-2 and radix-2² algorithms respectively, while achieving SQNR of more than 55dB without increasing the internal wordlength progressively.

• Journal of Sensor Science and Technology
• /
• v.32 no.4
• /
• pp.246-251
• /
• 2023

Internet of Things (IoT) systems process signals from various sensors using signal processing algorithms suitable for the signal characteristics. To analyze complex signals, these systems usually use signal processing algorithms in the frequency domain, such as fast Fourier transform (FFT), filtering, and short-time Fourier transform (STFT). In this study, we propose a multi-mode sensor signal processor (SSP) accelerator with an FFT-based hardware design. The FFT processor in the proposed SSP is designed with a radix-2 single-path delay feedback (R2SDF) pipeline architecture for high-speed operation. Moreover, based on this FFT processor, the proposed SSP can perform filtering and STFT operation. The proposed SSP is implemented on a field-programmable gate array (FPGA). By sharing the FFT processor for each algorithm, the required hardware resources are significantly reduced. The proposed SSP is implemented and verified on Xilinxh's Zynq Ultrascale+ MPSoC ZCU104 with 53,591 look-up tables (LUTs), 71,451 flip-flops (FFs), and 44 digital signal processors (DSPs). The FFT, filtering, and STFT algorithm implementations on the proposed SSP achieve 185x average acceleration.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.9 no.1
• /
• pp.39-45
• /
• 2009

OFDM is used for achieving a high-speed data transmission in mobile wireless communication systems. Conventionally, fast Fourier transform that is the main signal processing of OFDM is implemented using digital signal processing. The DSP FFT LSI requires large power consumption. Current-mode FFT LSI with analog signal processing is one of the best solutions for high speed and low power consumption. However, for the operation of current-mode FFT LSI that has the structure of parallel-input and parallel-output, current-mode serial-to-parallel and parallel-to-serial converter are indispensable. We propose a novel current-mode SPC and PSC and full chip simulation results agree with experimental data. The proposed current-mode SPC and PSC promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.2
• /
• pp.97-105
• /
• 2015

This paper discusses the implementation of Bruun's FFT on a SIMD processor. FFT is an algorithm used in digital signal processing area and its effective processing is important in the enhancement of signal processing performance. Bruun's FFT algorithm is one of fast Fourier transform algorithms based on recursive factorization. Compared to popular Cooley-Tukey algorithm, it is advantageous in computations because most of its operations are based on real number multiplications instead of complex ones. However it shows more complicated data alignment patterns and requires a larger memory for storing coefficient data in its implementation on a SIMD processor. According to our experiment result, in the processing of the FFT with 1024 complex input data on a SIMD processor, The Bruun's algorithm shows approximately 1.2 times higher throughput but uses approximately 4 times more memory (20 Kbyte) than the Cooley-Tukey algorithm. Therefore, in the case with loose constraints on silicon area, the Bruun's algorithm is proper for the processing of FFT on a SIMD processor.

• IEIE Transactions on Smart Processing and Computing
• /
• v.3 no.6
• /
• pp.372-381
• /
• 2014

This study examined a radar signal active cancelation technique, which is a theoretical way of achieving stealth by employing a baseband process that involves sampling the incoming hostile radar signal, analyzing its characteristics, and generating countermeasure signals to cancel out the linear-FM signal of the hostile radar signal reflected from the airborne target. To successfully perform an active cancelation, the effects of errors in the countermeasure signal were first analyzed. To generate the countermeasure signal that requires very fast and accurate processing, the down-sampling technique with the suboptimal maximum likelihood estimation (sMLE) scheme was proposed to improve the speed of the estimation process while preserving the estimation accuracy. The simulation results showed that the proposed down-sampling technique using a 2048 FFT size yields substantial power reduction despite its small FFT size and exhibits similar performance to the sMLE scheme using the 32768 FFT size.

• Journal of the Korea Institute of Military Science and Technology
• /
• v.9 no.3
• /
• pp.116-122
• /
• 2006

A fast scan digital-IF FFT receiver at the radio communication band is presented for spectrum monitoring applications. It is composed of three parts: RF front-end, fast LO board, and signal processing board. It has about 19GHz/s scan rate, multi frequency resolution from 10kHz to 2.5kHz, and high sensitivity of below -99dBm. The design and performance analysis of the digital-IF FFT receiver are presented.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.34 no.1
• /
• pp.11-19
• /
• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.5
• /
• pp.229-234
• /
• 2010

This paper proposed the acoustic signal processing techniques, which are applicable even in the shallow river, and will enhance the frequency resolution of the ADCP (Acoustic Doppler Current profiler). ADCP is a device that measures the velocity of a moving fluid. ADCP, in general, can be operated at ~300 Khz of center frequency due to no depth limit in the sea. However, it can hardly be used due to water depth of 30cm or shallower during the dry season in the river. Therefore, existing signal processing methods are not suitable to use in the shallow river. We are proposing an alternative acoustic signal processing method using Zoom FFT. Simulation results show that errors are reduced ${\pm}62\;cm/s$ in theory, and ${\pm}93\;cm/s$ in the experiment. The existing algorithm could not estimate the current speed at the shallow river below 30 cm, but proposed algorithm estimated the current speed that was faster than 20 cm/s at the shallow river below 30 cm.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.62-71
• /
• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.