• Title/Summary/Keyword: FET device

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Design and Implementation of a Motor Power Change Speed Device for Micro-controller (Micro-controller 방식에 의한 Motor Power 변속장치의 설계와 구현)

  • 김정래
    • Journal of the Korea Society of Computer and Information
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    • v.8 no.3
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    • pp.163-169
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    • 2003
  • This study was carried out develope a motor power change speed device of motor by used micro- controller. This system was producted a auto-change speed device which switching frequency was 1,000MHz by used a auto- controller. It had a continuous output current such as 5A, 11A, 25A, 35A, 50A. It used a variable voltage from 9V to 18V(Maximum). We designed hardware of and software of micro-controller, we are made up of a auto cut-off function by 3.7V for detected power-loss prevention.

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Thermal Resistance Characteristics and Fin-Layout Structure Optimization by Gate Contact Area of FinFET and GAAFET (FinFET 및 GAAFET의 게이트 접촉면적에 의한 열저항 특성과 Fin-Layout 구조 최적화)

  • Cho, Jaewoong;Kim, Taeyong;Choi, Jiwon;Cui, Ziyang;Xin, Dongxu;Yi, Junsin
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.34 no.5
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    • pp.296-300
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    • 2021
  • The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO

  • Boukortt, Nour El Islam;Hadri, Baghdad;Caddemi, Alina;Crupi, Giovanni;Patane, Salvatore
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.3
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    • pp.156-161
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    • 2015
  • In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φm. As a consequence, the behavior of the leakage current improves with increased Φm. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

A Basic Study on the Low Drift Flux Meter by Using a Peltier Device (펠티어 소자를 사용한 Low Drift Flux Meter의 기초연구)

  • Kim, Chul-Han;Heo, Jin;Shin, kwang-Ho;Sa-Gong, Geon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.11
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    • pp.912-916
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    • 2001
  • Fluxmeter is a measuring instrument the magnetic flux intensity by means of an integration of the voltage induced to a search coil to unit time. It also is required to a precise integrator since the voltage induced to a search coil has a differential value of the flux ${\Phi}$ to unit time. In this study, a bias current which is a main problem of the integrator in a drift troublesome depending on the temperature of a FET is investigated. We have confirmed that the temperature dependence of both the bias current of a integrator using the FET and the reversal saturated current of the minor carrier in a P-N junction of a semiconductor were the same. The property of a commercial integrator goes rapidly down with increasing temperature. The bias current of a FET is increased twice as much with 10$^{\circ}C$ increment. As a result, the low drift integrator could be developed by setting the lower temperature up with a pottier device.

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Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

  • Yu, Byoung-Gon;You, In-Kyu;Lee, Won-Jae;Ryu, Sang-Ouk;Kim, Kwi-Dong;Yoon, Sung-Min;Cho, Seong-Mok;Lee, Nam-Yeal;Shin, Woong-Chul
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.2 no.3
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    • pp.213-225
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    • 2002
  • Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

Fabrication of SOI FinFET devices using Aresnic solid-phase-diffusion (비소 고상확산방법을 이용한 MOSFET SOI FinFET 소자 제작)

  • Cho, Won-Ju;Koo, Hyun-Mo;Lee, Woo-Hyun;Koo, Sang-Mo;Chung, Hong-Bay
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2006.11a
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    • pp.133-134
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    • 2006
  • A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

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Easy Detection of Amyloid β-Protein Using Photo-Sensitive Field Effect

  • Kim, Kwan-Soo;Ju, Jong-Il;Song, Ki-Bong
    • Journal of Sensor Science and Technology
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    • v.21 no.5
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    • pp.339-344
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    • 2012
  • This article describes a novel method for the detection of amyloid-${\beta}$($A{\beta}$) peptide that utilizes a photo-sensitive field-effect transistor (p-FET). According to a recent study, $A{\beta}$ protein has been known to play a central role in the pathogenesis of Alzheimer's disease (AD). Accordingly, we investigated the variation of photo current generated from p-FET with and without intracellular magnetic beads conjugated with $A{\beta}$ peptides, which are placed on the p-FET sensing areas. The decrease of photo current was observed due to the presence of the magnetic beads on the channel region. Moreover, a similar characteristic was shown when the Raw 264 cells take in magnetic beads treated with $A{\beta}$ peptide. This means that it is possible to simply detect a certain protein using magnetic beads and a p-FET device. Therefore, in this paper, we suggest that our method could detect tiny amounts of $A{\beta}$ for early diagnosis of AD using the p-FET devices.

Current-Voltage and Conductance Characteristics of Silicon-based Quantum Electron Device (실리콘 양자전자소자의 전류-전압 및 컨덕턴스 특성)

  • Seo, Yong-Jin
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.811-816
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    • 2019
  • The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

Next-Generation Frozen Elephant Trunk Technique in the Era of Precision Medicine

  • Suk-Won Song;Ha Lee;Myeong Su Kim;Randolph Hung Leung Wong;Jacky Yan Kit Ho;Wilson Y. Szeto;Heinz Jakob
    • Journal of Chest Surgery
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    • v.57 no.5
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    • pp.419-429
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    • 2024
  • The frozen elephant trunk (FET) technique can be applied to extensive aortic pathology, including lesions in the aortic arch and proximal descending thoracic aorta. FET is useful for tear-oriented surgery in dissections, managing malperfusion syndrome, and promoting positive aortic remodeling. Despite these benefits, complications such as distal stent-induced new entry and spinal cord ischemia can pose serious problems with the FET technique. To prevent these complications, careful sizing and planning of the FET are crucial. Additionally, since the FET technique involves total arch replacement, meticulous surgical skills are essential, particularly for young surgeons. In this article, we propose several techniques to simplify surgical procedures, which may lead to better outcomes for patients with extensive aortic pathology. In the era of precision medicine, the next-generation FET device could facilitate the treatment of complex aortic diseases through a patient-tailored approach.

Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs (부분 채널도핑된 GaAs계 이중이종접합 전력FET의 선형성 증가)

  • Kim, U-Seok;Kim, Sang-Seop;Jeong, Yun-Ha
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.1
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    • pp.83-88
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    • 2002
  • To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.