• Title/Summary/Keyword: FET Device

Search Result 259, Processing Time 0.025 seconds

Micro-controller 방식에 의한 Motor Power 변속장치의 설계와 구현 (Design and Implementation of a Motor Power Change Speed Device for Micro-controller)

  • 김정래
    • 한국컴퓨터정보학회논문지
    • /
    • 제8권3호
    • /
    • pp.163-169
    • /
    • 2003
  • 본 연구에서 개발하고자 하는 기기의 모델은 마이크로 컨트롤을 이용하여 모터속도를 제어 할 수 있는 출력 전자 변속기로써, 자동제어 방식을 사용하여 Switching frequency를 1,000MHz까지 가능한 형태로 변환하는 자동 변속장치이다. 연속출력전류는 5A, 11A, 18A, 25A, 35A, 50A이며, 사용되는 전압은 9V에서 최대 18V까지 가능하도록 설계하였다. Micro-controller 의 software와 hardware의 블록 다아이그램을 고안하였으며, 전력손실을 막기 위해 자동적으로 3.7V에서 Auto Cut-Off기능이 있도록 구성하였다.

  • PDF

FinFET 및 GAAFET의 게이트 접촉면적에 의한 열저항 특성과 Fin-Layout 구조 최적화 (Thermal Resistance Characteristics and Fin-Layout Structure Optimization by Gate Contact Area of FinFET and GAAFET)

  • 조재웅;김태용;최지원;최자양;신동욱;이준신
    • 한국전기전자재료학회논문지
    • /
    • 제34권5호
    • /
    • pp.296-300
    • /
    • 2021
  • The performance of devices has been improved with fine processes from planar to three-dimensional transistors (e.g., FinFET, NWFET, and MBCFET). There are some problems such as a short channel effect or a self-heating effect occur due to the reduction of the gate-channel length by miniaturization. To solve these problems, we compare and analyze the electrical and thermal characteristics of FinFET and GAAFET devices that are currently used and expected to be further developed in the future. In addition, the optimal structure according to the Fin shape was investigated. GAAFET is a suitable device for use in a smaller scale process than the currently used, because it shows superior electrical and thermal resistance characteristics compared to FinFET. Since there are pros and cons in process difficulty and device characteristics depending on the channel formation structure of GAAFET, we expect a mass-production of fine processes over 5 nm through structural optimization is feasible.

3-D Simulation of Nanoscale SOI n-FinFET at a Gate Length of 8 nm Using ATLAS SILVACO

  • Boukortt, Nour El Islam;Hadri, Baghdad;Caddemi, Alina;Crupi, Giovanni;Patane, Salvatore
    • Transactions on Electrical and Electronic Materials
    • /
    • 제16권3호
    • /
    • pp.156-161
    • /
    • 2015
  • In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φm. As a consequence, the behavior of the leakage current improves with increased Φm. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

펠티어 소자를 사용한 Low Drift Flux Meter의 기초연구 (A Basic Study on the Low Drift Flux Meter by Using a Peltier Device)

  • 김철한;허진;신광호;사공건
    • 한국전기전자재료학회논문지
    • /
    • 제14권11호
    • /
    • pp.912-916
    • /
    • 2001
  • Fluxmeter is a measuring instrument the magnetic flux intensity by means of an integration of the voltage induced to a search coil to unit time. It also is required to a precise integrator since the voltage induced to a search coil has a differential value of the flux ${\Phi}$ to unit time. In this study, a bias current which is a main problem of the integrator in a drift troublesome depending on the temperature of a FET is investigated. We have confirmed that the temperature dependence of both the bias current of a integrator using the FET and the reversal saturated current of the minor carrier in a P-N junction of a semiconductor were the same. The property of a commercial integrator goes rapidly down with increasing temperature. The bias current of a FET is increased twice as much with 10$^{\circ}C$ increment. As a result, the low drift integrator could be developed by setting the lower temperature up with a pottier device.

  • PDF

Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

  • Yu, Byoung-Gon;You, In-Kyu;Lee, Won-Jae;Ryu, Sang-Ouk;Kim, Kwi-Dong;Yoon, Sung-Min;Cho, Seong-Mok;Lee, Nam-Yeal;Shin, Woong-Chul
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • 제2권3호
    • /
    • pp.213-225
    • /
    • 2002
  • Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

비소 고상확산방법을 이용한 MOSFET SOI FinFET 소자 제작 (Fabrication of SOI FinFET devices using Aresnic solid-phase-diffusion)

  • 조원주;구현모;이우현;구상모;정홍배
    • 한국전기전자재료학회:학술대회논문집
    • /
    • 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
    • /
    • pp.133-134
    • /
    • 2006
  • A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

  • PDF

Easy Detection of Amyloid β-Protein Using Photo-Sensitive Field Effect

  • Kim, Kwan-Soo;Ju, Jong-Il;Song, Ki-Bong
    • 센서학회지
    • /
    • 제21권5호
    • /
    • pp.339-344
    • /
    • 2012
  • This article describes a novel method for the detection of amyloid-${\beta}$($A{\beta}$) peptide that utilizes a photo-sensitive field-effect transistor (p-FET). According to a recent study, $A{\beta}$ protein has been known to play a central role in the pathogenesis of Alzheimer's disease (AD). Accordingly, we investigated the variation of photo current generated from p-FET with and without intracellular magnetic beads conjugated with $A{\beta}$ peptides, which are placed on the p-FET sensing areas. The decrease of photo current was observed due to the presence of the magnetic beads on the channel region. Moreover, a similar characteristic was shown when the Raw 264 cells take in magnetic beads treated with $A{\beta}$ peptide. This means that it is possible to simply detect a certain protein using magnetic beads and a p-FET device. Therefore, in this paper, we suggest that our method could detect tiny amounts of $A{\beta}$ for early diagnosis of AD using the p-FET devices.

실리콘 양자전자소자의 전류-전압 및 컨덕턴스 특성 (Current-Voltage and Conductance Characteristics of Silicon-based Quantum Electron Device)

  • 서용진
    • 전기전자학회논문지
    • /
    • 제23권3호
    • /
    • pp.811-816
    • /
    • 2019
  • 초고진공 화학기상증착장치(UHV-CVD)에 의해 성장된 실리콘-흡착된 산소(Si-O) 초격자가 실리콘 양자전자소자를 위한 에피택셜 장벽으로 소개되었다. 전류-전압 측정 결과 높은 브레이크다운 전압을 갖는 매우 안정하고 양호한 절연특성을 나타내었다. 에피택셜 성장된 Si-O 초격자는 SOI(silicon on insulator)를 대체할 수 있는 절연층으로도 사용될 수 있음을 보여준다. 이 두꺼운 장벽은 전계효과트랜지스터(FET)의 절연 게이트로 유용하게 사용될 수 있어 FET 위에 또 다른 FET를 제작할 수 있으므로 미래 실리콘계 3차원 집적회로의 궁극적인 목표에 한층 더 다가갈 수 있는 가능성을 보여주는 것이다.

Next-Generation Frozen Elephant Trunk Technique in the Era of Precision Medicine

  • Suk-Won Song;Ha Lee;Myeong Su Kim;Randolph Hung Leung Wong;Jacky Yan Kit Ho;Wilson Y. Szeto;Heinz Jakob
    • Journal of Chest Surgery
    • /
    • 제57권5호
    • /
    • pp.419-429
    • /
    • 2024
  • The frozen elephant trunk (FET) technique can be applied to extensive aortic pathology, including lesions in the aortic arch and proximal descending thoracic aorta. FET is useful for tear-oriented surgery in dissections, managing malperfusion syndrome, and promoting positive aortic remodeling. Despite these benefits, complications such as distal stent-induced new entry and spinal cord ischemia can pose serious problems with the FET technique. To prevent these complications, careful sizing and planning of the FET are crucial. Additionally, since the FET technique involves total arch replacement, meticulous surgical skills are essential, particularly for young surgeons. In this article, we propose several techniques to simplify surgical procedures, which may lead to better outcomes for patients with extensive aortic pathology. In the era of precision medicine, the next-generation FET device could facilitate the treatment of complex aortic diseases through a patient-tailored approach.

부분 채널도핑된 GaAs계 이중이종접합 전력FET의 선형성 증가 (Linearity Enhancement of Partially Doped Channel GaAs-based Double Heterostructure Power FETs)

  • 김우석;김상섭;정윤하
    • 대한전자공학회논문지SD
    • /
    • 제39권1호
    • /
    • pp.83-88
    • /
    • 2002
  • HFET 소자의 선형성과 게이트-트레인 항복특성을 향상시키기 위해 부분채널 도핑된 Al/sub 0.25/Ga/sub 0.75/As/In/sub 0.25/Ga/sub 0.75/As/Al/sub 0.25/Ga/sub 0.75/As 이종접합 구조를 갖는 FET를 제안하였다. 제안된 HFET는 게이트 전극 아래로 도핑되지 않은 AlGaAs 진성공급층을 두어 -2OV 의 높은 항복전압을 얻었다. 또한 소자의 InGaAs 채널에 부분 도핑을 실시하여, 균일 채널 도핑을 실시한 경우보다 향상된 선형성을 유도하였고, 2차원 전산모사 견과와 제작 및 측정결과를 통해 선형성의 향상을 확인하였다. 본 실험에서 제안된 HFET소자는 DC측정 결과와 고주파측정 결과 모두에서 기존의 FET소자들에 비해 향상된 선형성을 나타내었다.