• Journal of the Korea Society of Computer and Information
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• v.5 no.2
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• pp.115-120
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• 2000

This papers describes two low-noise amplifiers that use the Hewlett-Packard ATF-10236 low noise GaAs FET device, The actual measured performance of the amplifiers compares favorably to that predicted by the computer simulation(ADS) the noise figure of the 1575MHz amplifier was measured at 1.78dB which is lower that 2dB as specified. Measurement gam measured 33.0075dB which is within 35dB$\pm$0.5㏈ of the GPS specification. Network Analyzer(HP8510) is used to measure all the s-parameters and Noise Figure meter(HP8970B) is used to measure noise figure. As the result of experiment, gain, input VSWR, output VSWR is within the GPS specification sufficiently.

• Journal of IKEEE
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• v.14 no.4
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• pp.277-282
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• 2010

In this paper, we proposed ZnO trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, ZnO and SiC power devices is next generation power semiconductor devices. We carried out modeling of ZnO SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.63-63
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• 2010

Ability to transport extracted carriers from NQDs is essential for the development of most NQD based applications. Strategies to facilitate carrier transport while preserving NQDs' optical characteristics include: 1) Fabricating neat films of NQDs with modified surfaces either by adapting series of ligands with certain limitations or by applying physical processes such as heat annealing 2) Coupling of NQDs to one-dimensional nanostructures such as single walled carbon nanotubes (SWNTs) or various types of nanowires. NQD-nanowire hybrid nanostructures are expected to facilitate selective wavelength absorption, charge transfer to 1-D nanostructures, and efficient carrier transport. Even with the vast interests in using NQD-SWNT hybrid materials in optoelectric applications, still, no reports so far have clearly elucidated the optoelectric behavior when they were assembled on the FET mainly because the complexity involving in both components in their preparation and characterization. We have monitored the optical properties of both components (NQDs, SWNTs) from the synthesis, to the assembly, and to the device. More importantly, by using pyridine molecules as a linker to non-covalently attach NQDs to SWNTs, we were able to assemble NQDs on SWNTs with precise density control without harming their electronic structures. Furthermore, by measuring electrical signals from the fabricated aligned SWNTs-FET using dielectrophoresis (DEP), we were able to elucidate the charge transfer mechanism.

• Applied Microscopy
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• v.52
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• pp.1.1-1.8
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• 2022

As semiconductor device architecture develops, from planar field-effect transistors (FET) to FinFET and gate-all-around (GAA), there is an increased need to measure 3D structure sidewalls precisely. Here, we present a 3-Dimensional Atomic Force Microscope (3D-AFM), a powerful 3D metrology tool to measure the sidewall roughness (SWR) of vertical and undercut structures. First, we measured three different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with a relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. All analysis was performed using a novel algorithm, including auto fattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The results suggest that our 3D-AFM, based on the tilted Z scanner, will enable an advanced methodology for automated 3D measurement and analysis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1717-1723
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• 2007

In this study , quasi-MFISFET (Metal-Ferroelectric-Insulator-Semiconductor FET) devices are fabricated using PLZT(10/30/70), PLT(10), PZT(30/70) thin film and their drain current properties are investigated. It is found that the drain current of quasi-MFISFET is directly influenced by the polarization strength of ferroelectric thin fan. Also, when the gate voltages are ${\pm}5\;and\;{\pm}10V$, the memory windows are 0.5 and 1.3V, respectively. It means that the memory window is changed with the variation of coercive voltage generated by the voltage applied on ferroelectric thin film. The electric field and the leakage current with time delay of PLZT(10/30/70) thin lam are measured to investigate the retention property of MFISFET device. Some material parameters such as current density constant, $J_{ETO}$, electric field dependent factor K and time dependent factor m are obtained. The variation of charge density with time is quantitatively analyzed by using the material parameters.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.204-209
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• 2017

We have investigated a Mo/Au gate scheme for use in AlGaN/GaN-on-Si HFETs. AlGaN/GaN-on-Si HFETs were fabricated with Ni/Au or Mo/Au gates and their electrical characteristics were compared after thermal stress tests. While insignificant difference was observed in DC characteristics, the Mo/Au gate device exhibited lower on-resistance with superior pulsed characteristics in comparison with the Ni/Au gate device.

• Journal of Sensor Science and Technology
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• v.23 no.6
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• pp.392-396
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• 2014

The 2-dimensional silicon vertical Hall devices, which are sensitive to X,Y components of the magnetic field parallel to the surface of the chip, are fabricated using a modified bipolar process. It consists of the thin p-layer at Si-$SiO_2$ interface and n-epi layer to improve the sensitivity and influence of interface effect. Experimental samples are a sensor type K with and type J without $p^+$ isolation dam adjacent to the center current electrode. The results for both type show a more high sensitivity than the former's 2-dimensional vertical Hall devices and a good linearity. The measured non-linearity is about 0.8%. The sensitivity of type J and type K are about 66 V/AT and 200 V/AT, respectively. This sensor's behavior can be explained by the similar J-FET model.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.192.1-192.1
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• 2015

We demonstrated the nonvolatile memory functionality of nano-crystalline silicon (nc-Si) and InGaZnOxide (IGZO) thin film transistors (TFTs) using mobile protons that are generated by very short time hydrogen neutral beam (H-NB) treatment in gate insulator (SiO2). The whole memory fabrication process kept under $50^{\circ}C$ (except SiO2 deposition process; $300^{\circ}C$). These devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We also executed hydrogen treatment in order to figure out the difference of mobile proton generation between PECVD and H-NB CVD that we modified. Our study will further provide a vision of creating memory functionality and incorporating proton-based storage elements onto a probability of next generation flexible memorable electronics such as low power consumption flexible display panel.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.85-88
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• 1995

In this report the large-signal RF performance of GaN MESFETs at different operating temperatures is investigated using a harmonic balance modeling technique. The predicted device performance calculated by the large-si anal model of a GaN FET is shown to be in good agreement with experimen tar data. It is demonstrated that the optimal RF performance of a GaN MESFET amplifier is achieved by balancing the input impedence for a optimized de sign. A GaN MESFET with the optimized design is predicted to produce maximum RF output power of about 4W/mm and 1W/mm at room temperature and 773 K, respectively. The device produces a peak Power-Added Efficiency (PAE) of 52% and 32% at the two temperatures.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.55-58
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• 1998

Recently, neural networks with self-adaptability like human brain have attracted much attention. It is desirable for the neuron-function to be implemented by exclusive hardware system on account of huge quantity in calculation. We have proposed a novel neuro-device composed of a MFSFET(ferroelectric gate FET) and oscillation circuit with CUJT(complimentary unijuction transistor) and PUT(programmable unijuction transistor). However, it is difficult to preserve ferroelectricity on Si due to existence of interfacial traps and/or interdiffusion of the constitutent elements, although there are a few reports on good MFS devices. In this paper, we have simulated CUJT and PUT devices instead of fabricating them and composed oscillation circuit. Finally, we have resented, as an approach to the MFSFET neuron circuit, adaptive learning function and characterized the elementary operation properties of the pulse oscillation circuit.