• EDISON SW 활용 경진대회 논문집
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• 제6회(2017년)
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• pp.412-416
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• 2017

CMOS device에서 off leakage current로 인한 power dissipation 문제는 미래 소자에 주어진 주요한 과제이다. Nanowire FET은 이러한 문제를 해결할 주요 미래소자로 각광받고있다. 하지만 nanowire FET을 공정할 때 채널 에칭을 완벽한 원형 구조로 가지는 것이 어렵기 때문에 타원형으로 시뮬레이션을 진행해 볼 필요성이 있다. 본 논문에서는 nanowire의 aspect ratio, crystal orientation의 변화에 따른 nanowire FET의 전압-전류 특성 및 transport 특성을 관찰하는 연구를 진행하였다. 시뮬레이션 결과, [100] 방향은 완벽한 원형구조에서 최적인 반면에 [110] 방향은 타원형으로 모델링함에 있어서 장점이 있는 것으로 나타났다.

• 한국정보통신학회논문지
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• 제13권11호
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• pp.2373-2377
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• 2009

본 연구에서는 3차원 포아송방정식을 이용하여 FinFET의 문턱전압특성을 분석하였다. FinFET는 차세대 나노소자로서 단채널효과를 감소시킬 수 있다는 장점 때문에 많은 연구가 진행중에 있다. 이에 FinFET에서 단채널효과로서 잘 알려진 문턱 전압이하 스윙 및 문턱 전압 등을 3차원 포아송방정식의 분석학적 모델로 분석하고자 한다. 나노소자인 FinFET의 구조적 특성을 고찰하기 위하여 채널의 두께, 길이, 폭 등의 크기요소에 따라 분석하였다. 본 논문에서 사용한 분석학적 3차원 포아송방정식의 포텐셜모델 및 전송모델은 여러 논문에서 3차원 수치해석학적 값과 비교하여 그 타당성이 입증되었으므로 이 모델을 이용하여 FinFET의 문턱전압특성 및 문턱전압이하 특성을 분석하였다.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.389-393
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• 2007

We fabricated field-effect transistor based carbon nanotubes(CNTs) directly grown by thermal chemical vapor deposition(CVD) and analyzed their performance. The Ethylene ($C_2H_4$), hydrogen($H_2$) and Argon(Ar) gases were used for the growth of CNTs at $700\;^{\circ}C$. The growth properties of CNTs on the device were analyzed by SEM and AFM. The electrical transport characteristics of CNT FET were investigated by I-V measurement. Transport through the nanotubes is dominated by holes at room temperature. By varying the gate voltage, we successfully modulated the conductance of FET device by more than 7 orders of magnitude.

• 센서학회지
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• 제18권2호
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• pp.168-172
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• 2009

In this paper, we present the carbon nanotube field-effect transistor(CNT-FET) with a double-gate structure. A Carbon nanotube film was aligned by the Langmuir-Blodgett technique and $SiN_x$ was deposited to protect from water, oxygen, and other contaminants. We measured the electrical characteristics of the proposed device as the function of the $V_{BG}$, $V_{TG}$. From this result, we can confirm that proposed device might be employed as a biosensor.

• Transactions on Electrical and Electronic Materials
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• 제8권4호
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• pp.170-173
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• 2007

Organic field-effect transistors (OFETs) are of interest for use in widely area electronic applications. We fabricated the organic field-effect transistor based a copper phthalocyanine (CuPc) as an active layer on the silicon substrate. The CuPc FET device was made a topcontact type and the substrate temperature was room temperature and $150^{\circ}C$. The CuPc thickness was 40 nm, and the channel length was $50{\mu}m$, channel width was 3 mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in CuPc FET and we calculated the effective mobility with each device. Also, we observed the AFM images with different substrate temperature.

• 전기전자학회논문지
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• 제22권4호
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• pp.1088-1092
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• 2018

In this paper, we propose a dual-mode frequency tripler using push-push and stacked FET structures. The proposed circuit can operate either in frequency multiplier mode or in amplifier mode. In the frequency multiplier mode, push-push frequency multiplication is achieved by allowing input signals with particular phase shifts. In the amplifier mode, the device operates as a distributed amplifier to obtain high gain. Also both modes were designed using stacked FET structure. The designed circuit showed frequency tripled output power of 9.7 dBm at 2.4 GHz with the input at 800 MHz. On the other hand, in the amplifier mode, the device showed 8.9 dB of gain to generate 19.5 dBm at 800 MHz.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 하계종합학술발표회논문초록집
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• pp.333-333
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• 2004

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.1-14
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• 2001

Current status and prospects of FET-type FeRAMs (ferroelectric random access memories) are reviewed. First, it is described that the most important issue for realizing FET-type FeRAMs is to improve the data retention characteristics of ferroelectric-gate FETs. Then, necessary conditions to prolong the retention time are discussed from viewpoints of materials, device structure, and circuit configuration. Finally, recent experimental results related to the FET-type memories are introduced, which include optimization of a buffer layer that is inserted between the ferroelectric film and a Si substrate, development of a new ferroelectric film with a small remnant polarization value, proposal and fabrication of a 1T2C-type memory cell with good retention characteristics, and so on.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.191-197
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• 2016

In this paper, we investigated the hotcarrier injection (HCI) mechanism, one of the most important reliability issues, in 10 nm node Input/Output (I/O) bulk FinFET. The FinFET has much intensive HCI damage in Fin-bottom region, while the HCI damage for planar device has relatively uniform behavior. The local damage behavior in the FinFET is due to the geometrical characteristics. Also, the HCI is significantly affected by doping profile, which could change the worst HCI bias condition. This work suggested comprehensive understanding of HCI mechanisms and the guideline of doping profile in 10 nm node I/O bulk FinFET.