• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.933-937
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• 2005

FCBGA가 마더보드에 실장된 후 솔더 조인트에 균열이 생기면 단선이 발생한다. 솔더 조인트의 신뢰성을 평가하기 위한 방법 중 전단강도시험(shear test)은 약한 솔더 조인트를 판별하기 어려워 양품 로트와 불량 로트를 구별할 수 없으며, 인장강도시험(pull test)은 솔더 볼의 위치별 산포가 크고, peel test는 품질을 정량적으로 나타낼 수 없는 등의 문제가 있다. 새로운 시험 방법은 Area Pull Test(이하 APT)라 명명했으며 peel test와 pull test를 합한 개념으로서, 시험 샘플을 만드는 과정은 peel test와 동일하다. 솔더 조인트의 인장강도 측정은 지그를 만들어서 FCBGA 전체를 당겨서 측정하였다. 샘플은 Ni도금 두께를 3, 5, 8 ${\mu}m$로 제작하여 불량(3${\mu}m$), 양품으로 구분하였고, 양품 또한 품질 수준을 두가지(5,8${\mu}m$)로 나누었다. 그 결과 peel test 기준에 의거한 불량, 양품을 정량적인 수치(인장강도)로 판별할 수 있었으며, 솔더 조인트의 파괴모드별 인장강도를 구분 할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.59-65
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• 2011

According to the trends of electronic package to be smaller, thinner and more integrative, Flip Chip Ball Grid Array (FCBGA) become more used for mobile phone. However, the flip chip necessarily generate the heat by the electrical resistance and generated heat is increased due to reduced distribution area of the heat in accordance with the miniaturization trend of the package. Thermal issues can result in problems of devices that are sensitive to temperature and stress. Then the heat can generate problems to the system. In this paper, in order to improve the thermal issues of FCBGA, thermal characteristics of FCBGA was analyzed qualitatively by using the general heat transfer module of Comsol 3.5a and In order to solve thermal issues, flip chip with new micro structure is proposed by the simulation. and also by comparing existing model and analyzing variables such as pitch, height of the pattern and shape of the heat spreader, the improvement of heat dissipation characteristics about 18% was confirmed.

• Journal of Welding and Joining
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• v.32 no.3
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• pp.53-59
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• 2014

The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.33-38
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• 2013

In this study, both a finite element analysis and an experimental analysis are executed to investigate the mechanical characteristics of dielectric material effects on warpage. Also, viscoelastic material properties are measured by DMA and are considered in warpage simulation. A finite element analysis is done by using both thermal elastic analysis and a thermo-viscoelastic analysis to predict the nonlinear effects. For experimental study, specimens warpage of non-symmetric structure with body size of $22.5{\times}22.5$ mm, $37.5{\times}37.5$ mm and $42.5{\times}42.5$ mm are measured under the reflow temperature condition. From the analysis results, experimental warpage is not similar to FEA results using thermal elastic analysis but similar to FEA results using thermo-viscoelastic analysis. Also, its effect on substrate warpage is increased as core thickness is decreased and body size is getting larger. These FEA and the experimental results show that the nonlinear characteristics of dielectric material play an important role on substrate warpage. Therefore, it is strongly recommended that non-linear behavior characteristics of a dielectric material should be considered to control warpage of FCBGA substrate under conditions of geometry, structure and manufacturing process and so on.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• The Safety technology
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• no.153
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• pp.16-17
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• 2010

삼성전기는 우리나라를 대표하는 첨단 전자부품을 생산하는 기업으로 "미래를 창조하는 첨단기술, 첨단부품"이라는 기치를 내걸고, 디지털 세상의 미래를 창조하고 있다. 이 중 부산시 강서구 송정동에 위치하고 있는 부산공장은 휴대폰용 기판, FCBGA 등의 기판과 MLCC를 전문적으로 생산해오고 있는 기업으로, 최근 적극적인 투자를 통해, 양산 전문기지에서 개발과 생산 등 현지 완결형 체제를 시너지 효과를 발휘하고 있다. 이곳의 안전을 책임지고 있는 유준승 안전관리자. 기술력에서 세계 최고이듯, 안전에 있어서도 세계 최고인 삼성전기주식회사를 만들고자 그는 오늘도 구슬땀을 흘리며 현장을 누비고 있다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.3
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• pp.45-52
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• 2011

It is known that test methods to evaluate solder joint reliability are die shock test, die shear test, 3points bending test, and thermal shock test. The present study investigated the effects of failure mode on 3 types (as-reflowed, $85^{\circ}C$/85%RH treatment, and $150^{\circ}C$/10hr aging) of solder joints for flip-chip BGA package by using various test methods. The test methods and configurations are reported in detail, i.e. die shock, die shear, 3points bending, and thermal shock test. We focus on the failure mode of solder joints under various tests. The test results indicate that die shock and die shear test method can reveal brittle fracture in flip-chip ball grid array (FCBGA) packages with higher sensitivity.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.75-80
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• 2013

According to advance of electronic packaging technology, electronic package becomes smaller. Miniaturization of package causes the temperature rise of package. This can degrade life of electronic device and generate the failure of electronic system. In this study, we proposed a new semi-embedded structure with micro pattern for maximizing heat dissipation. A proposed structure showed the characteristics which have maximum temperature lower than $20^{\circ}C$ compared with conventional structure. And also, in view of thermal stress and strain, our structure showed a remarkably low value compared with other ones. We expect that the new structure proposed in this work can be applied to an flip-chip package of the future.