• ETRI Journal
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• v.37 no.5
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Proceedings of the Acoustical Society of Korea Conference
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• 1987.11a
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• pp.79-81
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• 1987

In this paper we propose a fast adaptive least squares algorithm for linear phase FIR filters. The algorithm requires 10m multiplications per data point where m is the filter order. Both linear phase cases with constant phase delay and constant group delay are examined. Simulation results demonstrate that the proeposed algorithm is superior to the LMS gradient algorithm and the averaging scheme used for the modified fast Kalman algorithm.

• The KIPS Transactions:PartC
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• v.19C no.2
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• pp.99-118
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• 2012

In PMIPv6-based network, mobile nodes can be made smaller and lighter because the network nodes perform the mobility management-related functions on behalf of the mobile nodes. The one of the protocols, Fast Handovers for Proxy Mobile IPv6(FPMIPv6)[1] has studied by the Internet Engineering Task Force(IETF). Since FPMIPv6 adopts the entities and the concepts of Fast Handovers for Mobile IPv6(FMIPv6) in Proxy Mobile IPv6(PMIPv6), it reduces the packet loss. Conventional scheme has proposed that it cooperated with an Authentication, Authorization and Accounting(AAA) infrastructure for authentication of a mobile node in PMIPv6, Despite the best efficiency, without begin secured of signaling messages, PMIPv6 is vulnerable to various security threats such as the DoS or redirect attAcks and it can not support global mobility between PMIPv. In this paper, we analyze Kang-Park & ESS-FH scheme, and then propose an Enhanced Security scheme for FPMIPv6(ESS-FP). Based on the CGA method and the pubilc key Cryptography, ESS-FP provides the strong key exchange and the key independence in addition to improving the weaknesses for FPMIPv6. The proposed scheme is formally verified based on Ban-logic, and its handover latency is analyzed and compared with that of Kang-Park scheme[3] & ESS-FH and this paper propose inter-domain fast handover sheme for PMIPv6 using proxy-based FMIPv6(FPMIPv6).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.673-685
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• 2002

In this paper, we analyze the pros and cons of the fast power control to the forward link in the environments where mixed traffics of voice and data produce the transmitted/received power difference. We propose the Zone-based power control scheme that can improve the performance of the fast power control scheme in the viewpoint of the resource allocation. The proposed scheme is a mechanism that controls both the power and rate of non-realtime data traffics according to location distribution of the mobile stations. The scheme is based on the conventional fast power control scheme in the CDMA systems, and it adaptively controls the transmission rate of each data traffic. Zone-based rate control of data call brings about somewhat power margin to the call. As a result, the proposed scheme saves the power consumption of portables and reduces the amount of interference. With the proposed scheme, not only be extended the service coverage of high-rate traffic to the entire cell service coverage, but also the QoS of low-rate traffic can keep going through the service time, especially, in the situation that the amount of incoming interference is much larger. The experimental results show that the proposed scheme yields a improved performance compared with the conventional scheme in terms of the power consumption and traffic throughput of portables, especially, with the increasing number of high-rate data traffics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.1
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• pp.8-16
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• 2014

In this paper, we propose a fast and scalable flow mobility management scheme based on the flow-based stateful routing for the IP-based mobile networks. The proposed scheme employees the crossover flow routers as mobility anchors to perform the distributed flow-based mobility management of the moving terminals, while aims to reduce the long handoff delay and the processing overhead of the existing IP packet routing. We evaluated the performance of the proposed scheme and verified the superior performance of the proposed scheme by comparing with the results of IP-based mobility management schemes.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.1-9
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• 2020

In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

• Journal of Computing Science and Engineering
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• v.5 no.4
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• pp.324-330
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• 2011

To avoid collisions, IEEE 802.11 medium access control (MAC) uses predetermined inter-frame spaces and the random back-off process. However, the retransmission strategy of IEEE 802.11 MAC results in considerable time wastage. The hidden node problem is well known in wireless networks; it aggravates the consequences of time wastage for retransmission. Many collision prevention and recovery approaches have been proposed to solve the hidden node problem, but all of them have complex control overhead. In this paper, we propose a fast retransmission scheme as a recovery approach. The proposed scheme identifies collisions caused by hidden nodes and then allows retransmission without collision. Analysis and simulations show that the proposed scheme has greater throughput than request-to-send and clear-to-send (RTS/CTS) and a shorter average waiting time.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.10 no.2
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• pp.38-47
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• 2001

In this paper, a new scheme of adaptive-neuro control system is presented to implement real-time control of robot manipulator using Digital Signal Processors. Digital signal processors, DSPs, are micro-processors that are particularly developed for fast numerical computations involving sums and products of measured variables, thus it can be programmed and executed through DSPs. In addition, DSPs are as fast in computation as most 32-bit micro-processors and yet at a fraction of therir prices. These features make DSPs a viable computational tool in digital implementation of sophisticated controllers. Unlike the well-established theory for the adaptive control of linear systems, there exists relatively little general theory for the adaptive control of nonlinear systems. Adaptive control technique is essential for providing a stable and robust perfor-mance for application of robot control. The proposed neuro control algorithm is one of learning a model based error back-propagation scheme using Lyapunov stability analysis method.The proposed adaptive-neuro control scheme is illustrated to be a efficient control scheme for the implementation of real-time control of robot system by the simulation and experi-ment.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.