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http://dx.doi.org/10.9708/jksci.2020.25.03.001

Dead Block-Aware Adaptive Write Scheme for MLC STT-MRAM Caches  

Hong, Seokin (School of Computer Science and Engineering, Kyungpook National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.25, no.3, 2020 , pp. 1-9 More about this Journal
Abstract
In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.
Keywords
STT-MRAM; Cache; Memory; Microprocessor; Dead Block; Simulation;
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