• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.411-412
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.541-542
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• 2008

• IE interfaces
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• v.12 no.3
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• pp.437-447
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• 1999

Modeling and system development for the fabrication process in the semiconductor manufacturing is presented in this paper. Maximization of wafer production can be achieved by the wafer flow balance under high utilization of bottleneck machines. Relatively simpler model is developed for the fabrication line by considering main characteristics of logistics. Simulation system is developed to evaluate the line performance such as balance rate, utilization, WIP amount and wafer production. Scheduling rules and input rules are suggested, and tested on the simulation system. We have shown that there exists good combination of scheduling and input rules.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.621-622
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• 2009

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.3
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• pp.311-318
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• 2000

The importance of the semiconductor industry in Korea has been growing, but the manufacturers are experiencing two major problems: poor optimization of production and low localization ratio of production equipments. Due to the complex manufacturing processes and special features such as OTD (On Time Delivery) and LIPAS (Line Item Performance Against Schedule) possibilities, several attempts to apply MRP or spreadsheet have been failed to meet the expectations. This paper describes the computer modeling technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process, and to build an advanced manufacturing environments. The computer simulation models are built referring the FAB facilities of the National Inter - University Semiconductor Research Center to show the FAB processes and the functions of each process.

• Journal of the Korea Society for Simulation
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• v.11 no.3
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• pp.59-65
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• 2002

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. Project executed that use conveyor in bay semiconductor A line. But conveyor capability is lacking and rundown happened in equipment. Do design without normal simulation and conveyor system failed. The comparison is peformed through simulation using .AutoMod a window 98 based discrete system simulation software, as a tool for comparing performance of proposed layouts. In this research estimate optimum conveyor capability, there is the purpose.

• Natural Product Sciences
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• v.13 no.2
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• pp.135-139
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• 2007

Four anthocyanins were isolated from the acidic alcoholic extract of Syzygium cumini fruits growing in Egypt: Pelargonidin-3-O-glucoside, pelargonidin-3,5-O-diglucoside, cyanidin-3-O-malonyl glucoside, and delphenidin-3-O-glucoside. They were identified by the chromatographic, TLC and PC, and spectral analyses, UV, $^1$H-NMR and FAB/MS. The fruits were found to contain 0.03 gm % anthocyanins calculated on fresh weight basis calculated by spectrophotometric assay. Cytotoxic activity of total alcoholic extract of the fruits was performed against several types of tumor cell lines using the SRB assay. The tested extract exhibited significant cytotoxic activity for MCF7 (breast carcinoma cell line) (IC$_{50}$= 5.9 ${\mu}$g/mL), while the IC$_{50}$ was > 10 ${\mu}$g/mL for both Hela (Cervix carcinoma cell line), HEPG2 (liver carcinoma cell line), H460 (Lung carcinoma cell line) and U251 (Brain carcinoma cell line).

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2001.10a
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• pp.298-301
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• 2001

In semiconductor manufacturing, wafer fabrication is the most complicated and important process, which is composed of several hundreds of process steps and several hundreds of machines involved. The productivity of the manufacturing mainly depends on how well they control balance of WIP flow to achieve maximal throughput under short manufacturing cycle time. In this paper mathematical formulation is suggested for the stepper scheduling, in which cycle time reduction and maximal production is achieved.

• Journal of the Korea Society for Simulation
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• v.18 no.4
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• pp.219-225
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• 2009

The primary purpose of this study is to build computer models referring overall flow of complex and various semiconductor wafer manufacturing process and to implement a educational model which operates with a presentation tool showing device design. It is important that Korean semiconductor industries secure high competitive power on efficient manufacturing management and to develop technology continuously. Models representing the FAB processes and the functions of each process are developed for Seoul National University Semiconductor Research Center. However, it is expected that the models are effective as visually educational tools in Korean semiconductor industries. In addition, it is anticipated that these models are useful for semiconductor process courses in academia. Scalability and flexibility allow semiconductor manufacturers to customize the models and perform simulation education. Subsequently, manufacturers save budget.