• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1999년도 학술대회논문집-국제 전기방전 및 플라즈마 심포지엄 Proceedings of 1999 KIIEE Annual Conference-International Symposium of Electrical Discharge and Plasma
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• pp.114-118
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• 1999

This paper shows a structure for an electronic ballast of HID lamps. An electronic ballast for HID lamps usually employs a high-frequency resonant inverter and voltage-to-frequency converter to control the output. A half-bridge and series resonant circuit are chosen for the ballast. The inverter with V/F converter is modeled with a transfer function and a self-feedback controller is proposed. This structure is analyzed and the feedback gain is determined by using the inverter model. Experimental system is built with a commercial 250W high pressure sodium lamp and the results show a validity of the proposed ballast.

• 대한전기학회논문지
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• 제43권3호
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• pp.397-408
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• 1994

In this paper, a novel concept for a static three-phase to three-phase power converter for an AC drive with a unity power factor and reduced harmonics on the utility line is presented. The power circuit consists of two back-to-back connected six-pulse bridges having only a $\mu$F ceramic capacitor in the DC link. By controlling the active kpower balance between two bridges, the DC link voltage can be maintained within 20V deviation from the nominal value with the small ceramic capacitors regardless of the load variation even in the unbalanced source condition.

• 대한전기학회논문지
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• 제38권2호
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• pp.93-99
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• 1989

This paper describes Sinusoidal Wave-Variable Voltage Variable Fequency (SW-VVVF) system for the high efficiency drive of a 3-phase induction motor. SW-VVVF system consists of a 3-phase 24-pulse converter and a SPWM inverter. The converter with additional 2 tap diode circuits in interphase reactor reduces harmonics in input current. The SPWM inverter consists of an improved PLL system and a V/F controller, which reduces harmonics in output current and performs a high efficiency algorithm by maintaining a constant slip frequency and compensating for the velocity variation of the induction motor with the change of load. Therefore, this system reduces harmonics in input and output currents, and also can drive an induction motor with high efficiency in an economical way. We have proved its utility through experiment.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 B
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• pp.695-697
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• 1993

In this paper, a novel concept for a static three-phase to three-phase power converter for an AC drive with an unity power factor and reduced harmonics on the utility line is presented. The power circuit consists of two back-to-back connected six-pulse bridges having only a $5{\mu}F$ ceramic capacitor in the DC link. By controlling the active power balance between two bridges, the DC link voltage can be maintained within 20V deviation from the nominal value with the small ceramic capacitor regardless of the load variation even in the unbalanced source condition.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 하계학술대회 논문집 A
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• pp.535-538
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• 1994

In this paper, an isolated ZVS-PWM boost converter is proposed for single stage line conversion. For power factor correction, we used the half bridge topology at the primary side of isolation transformer permitting switching devices to operate under ZVS by using circuit parastics and operating at a fixed duty ratio near 50%. Thus the relatively continuous input current distortion and small size input filter are also achievable. The ZVS-PWM boost operation of the proposed converter can be achieved by using the boost inductor $L_f$, main switch $Q_3$, and simple auxiliary circuit at the secondary side of isolation transformer. The secondary side circuit differ from a conventional PWM boost converter by introduction a simple auxiliary circuit. The auxiliary circuit is actived only during a short switching transition time to create the ZVS condition for the main switch as that of the ZVT-PWM boost converter. With a single stage, it is possible to achieve a sinusoidal line current at unity power factor as well as the isolated 48V DC output. Comparing to the two stage schemes, overall effiency of the proposed converter is highly improved due to the effective ZVS of all devices as well as single stage power conversion. Thus, it can be operated at high switching frequency allowing use of small size input filter. Minimum voltage and current stress make it high power application possible.

• IEIE Transactions on Smart Processing and Computing
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• 제4권3호
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• pp.183-188
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• 2015

A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with $0.18{\mu}m$ complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.

• 전력전자학회논문지
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• 제17권4호
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• pp.306-314
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• 2012

In case of the conventional DC-AC inverter using two DC-DC converters with unipolar output capacitor voltages, for generating the AC output voltage, the output capacitor voltages of its each DC-DC converter must be higher than the DC input voltage. To solve this problem, this paper proposes a single-phase DC-AC inverter using two embedded Z-source converters with bipolar output capacitor voltages. The proposed inverter is composed of two embedded Z-source converters with common DC source and output AC load. The AC output voltage is obtained by the difference of the output capacitor voltages of each converter. Though the output capacitor voltage of converter is relatively low compared to the conventional method, it can be obtained the same AC output voltage. Moreover, by controlling asymmetrically the output capacitor voltage, the AC output voltage of the proposed system is higher than the DC input voltage. To verify the validity of the proposed system, a DSP(TMS320F28335) based single-phase embedded Z-source DC-AC inverter was made and the PSIM simulation was performed under the condition of the DC source 38V. As controlled symmetrically and asymmetrically the output capacitor voltages of each converter, the proposed inverter could produce the AC output voltage with sinusoidal waveform. Particularly, in case of asymmetric control, a higher AC output voltage was obtained. Finally, the efficiency of the proposed system was measured as 95% and 97% respectively in case of symmetric and asymmetric control.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.632-634
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• 2004

First for high-qualify images and reducing process-error and driving speed, the designed 8-bit data driving circuit consists of a constant transconductance bias circuit, D-F/Fs by shift registers using static transmission gates, 1st latch and 2nd latch by tristate inverters, level shifters, current steering segmented D/A converters by 4MSB thermometer decoder and 4LSB weighted type. Second, we designed gray amp for power saving. These data driving circuits are designed with $0.35-{\mu}m$ CMOS technologies at 3.3 V and 18 V power supplies and simulated with HSPICE.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2019년도 전력전자학술대회
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• pp.305-306
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• 2019

본 논문에서는 고전압 커패시터 충전용 3상 LCC 공진형 컨버터를 설계하고 제작하였다. 고전압 커패시터 충전시간과 충전전압간에 선형성을 확보하기 위하여 컨버터는 충전 전 구간에서 정전류원으로 동작하도록 설계되었다. 공진탱크 설계를 위해서 FHA(Fundamental Harmonic Analysis) 기법을 이용하여 첨예도(Q; Quality factor)와 기저 주파수 변동에 따른 입출력 전류이득특성을 도출하였고 이를 바탕으로 28.8kJ/s의 충전속도를 가지며 최대 충전전압은 10kV 인 3상 LCC 공진형 컨버터를 제작하였다. 제작된 컨버터는 10kV, 600kJ 규격의 12mF 고전압 커패시터를 이용한 충전 실험을 통해 설계의 타당성을 확인하였다.

• Journal of Power Electronics
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• 제14권5호
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• pp.890-898
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• 2014

Critical conduction mode boost power factor correction converters operating at the boundary of continuous conduction mode and discontinuous conduction mode have been widely used for power applications lower than 300W. This paper proposes an enhanced variable on-time control method for the critical conduction mode boost PFC converter to improve the total harmonic distortion characteristic. The inductor current, which varies according to the input voltage, is analyzed in detail and the optimal on-time is obtained to minimize the total harmonic distortion with a digital controller using a TMS320F28335. The switch on-time varies according to the input voltage based on the computed optimal on-time. The performance of the proposed control method is verified by a 100W PFC converter. It is shown that the optimized on-time reduces the total harmonic distortion about 52% (from 10.48% to 5.5%) at 220V when compared to the variable on-time control method.