• Journal of Mechanical Science and Technology
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• v.18 no.12
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• pp.2294-2302
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• 2004

The objective of this study is to obtain detailed information for the micro fabrication of lead frames by applying spray technology to wet etching process. Wet etching experiments were performed with different etching parameters such as injection pressure, distance from nozzle tip to etched substrate, nozzle pitch and etchant temperature. The characteristics of single and twin spray were measured to investigate the correlation between the spray characteristics and the etching characteristics. Drop size and velocity were measured by Phase-Doppler Anemometer (PDA). Four liquids of different viscosity were used to reveal the effects of viscosity on the spray characteristics. The results indicated that the shorter the distance from nozzle tip and the nozzle pitch, the larger etching factor became. The average etching factor had good positive correlation with average axial velocity and impact force. It was found that the etching characteristics depended strongly on the spray characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• ETRI Journal
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• v.45 no.1
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• pp.171-179
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• 2023

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13㎛-0.16㎛ to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.2
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• pp.128-131
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• 2004

In this study Bosch etching process repeating etch and deposition by STS-ICP ASEHR was evaluated. Fundamentally etch depth changes were affected by thickness of deposited PR, $SiO_2$ and depth, and pattern size on the substrate. However etch rates were observed to be changed by variable parameters such as platen power, coil power, and process pressure. Etch rate showed $1.2\mu{m}/min$ and sidewall profile showed $90\pm0.2^\circ$ with platen power 12W, coil power 500W, and etch/passivation cycle 6/7sec. It was confirmed that this result was very typical to Bosch process utilizing ICP.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.222-225
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• 2008

We proposed the dry etching process recipe for the fabrication of In-Ga-Zn-O (IGZO)-based oxide TFTs, in which the etching behaviors of IGZO films were systematically investigated when the etching gas mixtures and their mixing ratios were varied. Good device characteristics of the fabricated TFT were successfully confirmed.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.97-100
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• 2018

$NF_3$ Plasma etching of silicon was conducted by injecting only $NF_3$ gas into reactive ion etching. $NF_3$ Plasma etching was done in intermediate pressure. Silicon etching by $NF_3$ plasma in reactive ion etching was diagnosed through residual gas analyzer and optical emission spectroscopy. In plasma etching, optical emission spectroscopy is generally used to know what kinds of species in plasma. Also, residual gas analyzer is mainly to know the byproducts of etching process. Through experiments, the results of optical emission spectroscopy during silicon etching by $NF_3$ plasma was analyzed with connecting the results of etch rate of silicon and residual gas analyzer. It was confirmed that $NF_3$ plasma etching of silicon in reactive ion etching accords with the characteristic of reactive ion etching.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• Journal of Integrative Natural Science
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• v.5 no.1
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• pp.13-17
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• 2012

Changes of Fabry-Perot fringe patterns in porous silicon during etching process has been investigated. Four porous silicon samples were prepared with four different etch currents: (a) 10 $mA/cm^2$, (b) 30 $mA/cm^2$, (c) 50 $mA/cm^2$, (d) 100 $mA/cm^2$, respectively. Optical characterization of Fabry-Perot fringe pattern on porous silicon was achieved by Ocean optics 2000 spectrometer. The change of Fabry-Perot fringes was monitored and measured during the etching process. Fabry-Perot fringes pattern start to form after couple of minutes. As the etching time increased, more reflection peaks were observed. Its full width at half maximum (FWHM) decreased rapidly when the etching time increased.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.279-281
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• 1997

The properties of Platinum dry etching were investigated in MICP(Magnetized Inductively Coupled Plasma). The problem with Platinum etching is the redeposition of sputtered Platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned Platinum structure produce feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape.[1] Generally, $Cl_2$ plasma is used for the fence-free etching.[1][2][3] The main object of this study was to investigate a new process technology for the fence-free Pt etching. Platinum was etched with Ar plasma at the cryogenic temperature and with Ar/$SF_6$ plasma at room temperature. In cryogenic etching, the height of fence was reduced to 20% at $-190^{\circ}C$ compared with that of room temp., but the etch profile was not fence-free. In Ar/$SF_6$ Plasma, chemical reaction took part in etching process. The trend of properties of Ar/$SF_6$ Plasma etching is similar to that of $Cl_2$ Plasma etching. Fence-free etching was possible, but PR selectivity was very low. A new gas chemistry for fence-free Platinum etching was proposed in this study.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.664-667
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• 1997

For higher component density per chip, it is necessary to identify and control the semiconductor manufacturing process more stringently. Recently, neural networks have been identified as one of the most promising techniques for modeling and control of complicated processes such as plasma etching process. Since wafer states after each run using identical recipe may differ from each other, conventional neural network models utilizing input factors only cannot represent the actual state of process and equipment. In this paper, in addition to the input factors of the recipe, real-time tool data are utilized for modeling of 64M DRAM s-poly plasma etching process to reflect the actual state of process and equipment. For real-time tool data, we collect optical emission spectroscopy (OES) data. Through principal component analysis (PCA), we extract principal components from entire OES data. And then these principal components are included to input parameters of neural network model. Finally neural network model is trained using feed forward error back propagation (FFEBP) algorithm. As a results, simulation results exhibit good wafer state prediction capability after plasma etching process.