• Title/Summary/Keyword: Etching Process

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A Study on the Ohmic Contacts and Etching Processes for the Fabrication of GaSb-based p-channel HEMT on Si Substrate (Si 기판 GaSb 기반 p-채널 HEMT 제작을 위한 오믹 접촉 및 식각 공정에 관한 연구)

  • Yoon, Dae-Keun;Yun, Jong-Won;Ko, Kwang-Man;Oh, Jae-Eung;Rieh, Jae-Sung
    • Journal of IKEEE
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    • v.13 no.4
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    • pp.23-27
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    • 2009
  • Ohmic contact formation and etching processes for the fabrication of MBE (molecular beam epitaxy) grown GaSb-based p-channel HEMT devices on Si substrate have been studied. Firstly, mesa etching process was established for device isolation, based on both HF-based wet etching and ICP-based dry etching. Ohmic contact process for the source and drain formation was also studied based on Ge/Au/Ni/Au metal stack, which resulted in a contact resistance as low as $0.683\;{\Omega}mm$ with RTA at $320^{\circ}C$ for 60s. Finally, for gate formation of HEMT device, gate recess process was studied based on AZ300 developer and citric acid-based wet etching, in which the latter turned out to have high etching selectivity between GaSb and AlGaSb layers that were used as the cap and the barrier of the device, respectively.

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Development of New Etching Algorithm for Ultra Large Scale Integrated Circuit and Application of ICP(Inductive Coupled Plasma) Etcher (초미세 공정에 적합한 ICP(Inductive Coupled Plasma) 식각 알고리즘 개발 및 3차원 식각 모의실험기 개발)

  • 이영직;박수현;손명식;강정원;권오근;황호정
    • Proceedings of the IEEK Conference
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    • 1999.06a
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    • pp.942-945
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    • 1999
  • In this work, we proposed Proper etching algorithm for ultra-large scale integrated circuit device and simulated etching process using the proposed algorithm in the case of ICP (inductive coupled plasma) 〔1〕source. Until now, many algorithms for etching process simulation have been proposed such as Cell remove algorithm, String algorithm and Ray algorithm. These algorithms have several drawbacks due to analytic function; these algorithms are not appropriate for sub 0.1 ${\mu}{\textrm}{m}$ device technologies which should deal with each ion. These algorithms could not present exactly straggle and interaction between Projectile ions and could not consider reflection effects due to interactions among next projectile ions, reflected ions and sputtering ions, simultaneously In order to apply ULSI process simulation, algorithm considering above mentioned interactions at the same time is needed. Proposed algorithm calculates interactions both in plasma source region and in target material region, and uses BCA (binary collision approximation4〕method when ion impact on target material surface. Proposed algorithm considers the interaction between source ions in sheath region (from Quartz region to substrate region). After the collision between target and ion, reflected ion collides next projectile ion or sputtered atoms. In ICP etching, because the main mechanism is sputtering, both SiO$_2$ and Si can be etched. Therefore, to obtain etching profiles, mask thickness and mask composition must be considered. Since we consider both SiO$_2$ etching and Si etching, it is possible to predict the thickness of SiO$_2$ for etching of ULSI.

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A Study on ILD(Interlayer Dielectric) Planarization of Wafer by DHF (DHF를 적용한 웨이퍼의 층간 절연막 평탄화에 관한 연구)

  • Kim, Do-Youne;Kim, Hyoung-Jae;Jeong, Hae-Do;Lee, Eun-Sang
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.5
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    • pp.149-158
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    • 2002
  • Recently, the minimum line width shows a tendency to decrease and the multi-level increases in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. However there are several defects in CMF, such as micro-scratches, abrasive contaminations and non-uniformity of polished wafer edges. Wet etching process including spin-etching can eliminate the defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(Interlayer-Dielectric) was removed by CMP and wet etching process using DHF(Diluted HF) in order to investigate the possibility of planrization by wet etching mechanism. In the thin film wafer, the results were evaluated from the viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And the pattern step heights were also compared for the purpose of planarity characterization of the patterned wafer. Moreover, Chemical polishing process which is the wet etching process with mechanical energy was introduced and evaluated for examining the characteristics of planarization.

Dry Etching Using Atmospheric Plasma for Crystalline Silicon Solar Cells (대기압 플라즈마를 이용한 결정질 태양전지 표면 식각 공정)

  • Hwang, Sang Hyuk;Kwon, Hee Tae;Kim, Woo Jae;Choi, Jin Woo;Shin, Gi-Won;Yang, Chang-Sil;Kwon, Gi-Chung
    • Korean Journal of Materials Research
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    • v.27 no.4
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    • pp.211-215
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    • 2017
  • Reactive Ion Etching (RIE) and wet etching are employed in existing texturing processes to fabricate solar cells. Laser etching is used for particular purposes such as selective etching for grooves. However, such processes require a higher level of cost and longer processing time and those factors affect the unit cost of each process of fabricating solar cells. As a way to reduce the unit cost of this process of making solar cells, an atmospheric plasma source will be employed in this study for the texturing of crystalline silicon wafers. In this study, we produced the atmospheric plasma source and examined its basic properties. Then, using the prepared atmospheric plasma source, we performed the texturing process of crystalline silicon wafers. The results obtained from texturing processes employing the atmospheric plasma source and employing RIE were examined and compared with each other. The average reflectance of the specimens obtained from the atmospheric plasma texturing process was 7.88 %, while that of specimens obtained from the texturing process employing RIE was 8.04 %. Surface morphologies of textured wafers were examined and measured through Scanning Electron Microscopy (SEM) and similar shapes of reactive ion etched wafers were found. The Power Conversion Efficiencies (PCE) of the solar cells manufactured through each process were 16.97 % (atmospheric plasma texturing) and 16.29 % (RIE texturing).

An Environment-Friendly Surface Pretreatment of ABS Plastic for Electroless Plating Using Chemical Foaming Agents

  • Kang, Dong-Ho;Choi, Jin-Chul;Choi, Jin-Moon;Kim, Tae-Wan
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.174-177
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    • 2010
  • We have developed an environment-friendly etching process, an alternative to the dichromic acid etching process, as a pretreatment of acrylonitrile-butadiene-styrene (ABS) plastic for electroless plating. In order to plate ABS plastic in an electroless way, there should be fine holes on the surface of the ABS plastic to enhance mechanically the adhesion strength between the plastic surface and the plate. To make these holes, the surface was coated uniformly with dispersed chemical foaming agents in a mixture of environmentally friendly dispersant and solvent by the methods of dipping or direct application. The solvent seeps into just below the surface and distributes the chemical foaming agents uniformly beneath the surface. After drying off the surface, the surface was heated at a temperature well below the glass transition temperature of ABS plastic. By pyrolysis, the chemical foaming agents made fine holes on the surface. In order to discover optimum conditions for the formation of fine holes, the mixing ratio of the solvent, the dispersant and the chemical foaming agent were controlled. After the etching process, the surface was plated with nickel. We tested the adhesion strength between the ABS plastic and nickel plate by the cross-cutting method. The surface morphologies of the ABS plastic before and after the etching process were observed by means of a scanning electron microscope.

Characterization of Combined Micro- and Nano-structure Silicon Solar Cells using a POCl3 Doping Process

  • Jeong, Chaehwan;Kim, Changheon;Lee, Jonghwan;Yi, Junsin;Lim, Sangwoo;Lee, Suk-Ho
    • Current Photovoltaic Research
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    • v.1 no.1
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    • pp.69-72
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    • 2013
  • Combined nano- and micro-wires (CNMWs) Si arrays were prepared using PR patterning and silver-assisted electroless etching. A $POCl_3$ doping process was applied to the fabrication of CNMWs solar cells. KOH solution was used to remove bundles in CNMWs and the etching time was varied from 30 to 240 s. The lowest reflectance of 3.83% was obtained at KOH etching time of 30 s, but the highest carrier lifetime of $354{\mu}s$ was observed after the doping process at 60 s. At the same etching time, a $V_{oc}$ of 574 mV, $J_{sc}$ of $28.41mA/cm^2$, FF of 74.4%, and Eff. of 12.2% were achieved in the CNMWs solar cell. CNMWs solar cells have potential for higher efficiency by improving the post-process and surface-rear side structure.

Real-time malfunction detection of plasma etching process using EPD signal traces (EPD 신호궤적을 이용한 플라즈마 식각공정의 실시간 이상검출)

  • Cha, Sang-Yeob;Yi, Seok-Ju;Koh, Taek-Beom;Woo, Kwang-Bang
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.2
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    • pp.246-255
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    • 1998
  • This paper presents a novel method for real-time malfunction detection of plasma etching process using EPD signal traces. First, many reference EPD signal traces are collected using monochromator and data acquisition system in normal etching processes. Critical points are defined by applying differentiation and zero-crossing method to the collected reference signal traces. Critical parameters such as intensity, slope, time, peak, overshoot, etc., determined by critical points, and frame attributes transformed signal-to symbol of reference signal traces are saved. Also, UCL(Upper Control Limit) and LCL(Lower Control Limit) are obtained by mean and standard deviation of critical parameters. Then, test EPD signal traces are collected in the actual processes, and frame attributes and critical parameters are obtained using the above mentioned method. Process malfunctions are detected in real-time by applying SPC(Statistical Process Control) method to critical parameters. the Real-time malfunction detection method presented in this paper was applied to actual processes and the results indicated that it was proved to be able to supplement disadvantages of existing quality control check inspecting or testing random-selected devices and detect process malfunctions correctly in real-time.

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The study of Ag etching effect by adding compound on the lead frame process (Lead frame 공정 중 화합물에 따른 Ag 에칭효과)

  • 이경수;박수길
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.859-862
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    • 2001
  • This study describes a selective Ag etching solution for use with pattern on the surface of copper. This etching solution uses potassium iodide and potassium sulfate as the ligand that coordinates to the metal ions and ferricyanide as the oxidant. The etching rate was depended on the concentration of co-ligands and time. But the etching rate wasn't depended on the pH(2∼6), and oxidant(K$_3$Fe(CN)$\_$6/). Complete etching of silver can be achieved rapidly within 90sec for 4.46${\mu}$m thick metal films when aqueous solutions containing K$_3$Fe(CN)$\_$6/, K$_2$S$_2$O$\_$8/ and KI was used. This etching solution was characteristic of anisotropic etching.

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Fabrication of Hollow-type Silicon Microneedle Array Using Microfabrication Technology (반도체 미세공정 기술을 이용한 Hollow형 실리콘 미세바늘 어레이의 제작)

  • Kim, Seung-Kook;Chang, Jong-Hyeon;Kim, Byoung-Min;Yang, Sang-Sik;Hwang, In-Sik;Pak, Jung-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.12
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    • pp.2221-2225
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    • 2007
  • Hollow-type microneedle array can be used for painless, continuous and stable drug delivery through a human skin. The needles must be sharp and have sufficient length in order to penetrate the epidermis. An array of hollow-type silicon microneedles was fabricated by using deep reactive ion etching and HNA wet etching with two oxide masks. Isotropic etching was used to create tapered tips of the needles, and anisotropic etching of Bosch process was used to make the extended length and holes of microneedles. The microneedles were formed by three steps of isotropic, anisotropic, and isotropic etching in order. The holes were made by one anisotropic etching step. The fabricated microneedles have $170{\mu}m$ width, $40{\mu}m$ hole diameter and $230{\mu}m$ length.

Development of apparatus for Single-sided Wet Etching and its applications in Corrugated Membrane Fabrication

  • Kim, Junsoo;Moon, Wonkyu
    • Journal of Sensor Science and Technology
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    • v.30 no.1
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    • pp.10-14
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    • 2021
  • Wet etching is more economical than dry etching and provides a uniform etching depth regardless of wafer sizes. Typically, potassium hydroxide (KOH) and tetra-methyl-ammonium hydroxide (TMAH) solutions are widely used for the wet etching of silicon. However, there is a limit to the wet etching process when a material deposited on an unetched surface reacts with an etching solution. To solve this problem, in this study, an apparatus was designed and manufactured to physically block the inflow of etchants on the surface using a rubber O-ring. The proposed apparatus includes a heater and a temperature controller to maintain a constant temperature during etching, and the hydrostatic pressure of the etchant is considered for the thin film structure. A corrugation membrane with a diameter of 800 ㎛, thickness of 600 nm, and corrugation depth of 3 ㎛ with two corrugations was successfully fabricated using the prepared device.