• Korean Journal of Optics and Photonics
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• v.19 no.1
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• pp.20-24
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• 2008

A color filter was proposed and demonstrated by incorporating a subwavelength patterned 1-dimensional grating in poly silicon. It was produced by employing the laser interference lithography method, providing much wider effective area compared to the conventional e-beam lithography. A $SiO_2$ layer was introduced on top of the silicon grating layer as a mask for the etching of the silicon, facilitating the etching of the silicon layer. It was theoretically found that the selectivity of the filter was also improved thanks to the oxide layer. The parameters for the designed device include the grating pitch of 450 nm, the grating height of 100 nm and the oxide-layer height of 200 nm. As for the fabricated filter, the spectral pass band corresponded to the blue color centered at 470 nm and the peak transmission was about 40%. Within the effective area of $3{\times}3mm^2$, the variation in the relative transmission efficiency and in the center wavelength was less than 10% and 2 nm respectively. Finally, the influence of the angle of the incident beam upon the transfer characteristics of the device was investigated in terms of the rate of the relative transmission efficiency, which was found to be equivalent to 1.5%/degree.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.169-169
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• 2008

To keep pace with scaling trends of CMOS technologies, high-k metal oxides are to be introduced. Due to their high permittivity, high-k materials can achieve the required capacitance with stacks of higher physical thickness to reduce the leakage current through the scaled gate oxide, which make it become much more promising materials to instead of $SiO_2$. As further studying on high-k, an understanding of the relation between the etch characteristics of high-k dielectric materials and plasma properties is required for the low damaged removal process to match standard processing procedure. There are some reports on the dry etching of different high-k materials in ICP and ECR plasma with various plasma parameters, such as different gas combinations ($Cl_2$, $Cl_2/BCl_3$, $Cl_2$/Ar, $SF_6$/Ar, and $CH_4/H_2$/Ar etc). Understanding of the complex behavior of particles at surfaces requires detailed knowledge of both macroscopic and microscopic processes that take place; also certain processes depend critically on temperature and gas pressure. The choice of $BCl_3$ as the chemically active gas results from the fact that it is widely used for the etching o the materials covered by the native oxides due to the effective extraction of oxygen in the form of $BCl_xO_y$ compounds. In this study, the surface reactions and the etch rate of $Al_2O_3$ films in $BCl_3/Cl_2$/Ar plasma were investigated in an inductively coupled plasma(ICP) reactor in terms of the gas mixing ratio, RF power, DC bias and chamber pressure. The variations of relative volume densities for the particles were measured with optical emission spectroscopy (OES). The surface imagination was measured by AFM and SEM. The chemical states of film was investigated using X-ray photoelectron spectroscopy (XPS), which confirmed the existence of nonvolatile etch byproducts.

• Korean Journal of Materials Research
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• v.10 no.4
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• pp.295-300
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• 2000

Uniform silicon tip arrays were fabricated using the reactive ion etching followed by the reoxidation sharpening, and the effect of Pd-coated layer on electron emission characteristics was studied. The electron emission from Si field emitter arrays(FEAs) was a little, but improved by removing surface oxide on the FEA, but pronounced drastically by coating a $100-{\AA}-thick$ Pd metal layer. The turn-on voltage in the Pd-coated Si FEAs was reduced by 30 V in comparison with that in uncoated ones. This results from the increase of surface roughness at the tip apex by the Pd coating on Si FEA, via the decrease of the apex radius at which electrons are emitting. The Pd-coated emitters showed superior operating stability over a wide current range to that of the uncoated ones. This suggests that Pd coating enhances the high temperature stability and the surface inertness Si FEA.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.5
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• pp.217-222
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• 2023

The purpose of this paper was to synthesize a polymer organic hard mask that simplifies the manufacturing process, reduces process time significantly, and thereby lowers manufacturing costs. The results of measuring residual metals through vapor refining showed that 9-Naphthalen-1-ylcarbazole(9-NC) measured 101.75ppb in the 4th zone, 2-Naphthol (2-NA) measured 306.98ppb in the 5th zone, and 9-Fluorenone(9-F) measured between 129.05ppb across the 4th and 5th zones. After passing through a filtration system, the synthesized organic hard mask measured residual metals in the range of 9 to 7ppb. Additionally, the thermal analysis indicated a decrease of 2.78%, a molecular weight of 942, carbon content of 89.74%, and a yield of 72.4%. The etching rate was measured at an average of 18.22Å/s, and the coating thickness deviation was averaged at 1.19. For particle sizes below 0.2㎛ in the organic hard mask, no particles were observed. By varying the coating speed at 1,000, 1,500, and 1,800rpm and measuring the resulting coating thickness, the shrinkage rate ranged from 17.9% to 20.8%. The coating results demonstrated excellent adhesion to SiON, and it was evident that the organic hard mask was uniformly applied.

• Journal of IKEEE
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• v.12 no.3
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• pp.138-143
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• 2008

In this study, we propose that the structures of spiral inductors have the environment advantage utilizing direct-write and LAM(Laser Ablation of Microparticles) processes without process step of lithography and etching etc. of existing semiconductor process. The structures of inductors have Si thickness of 540${\mu}m$, $SiO_2$ thickness of 3${\mu}m$. The width of Cu coils and the space between segments have 30${\mu}m$, respectively, using for direct-write and LAM processes. The performance of spiral planar inductors was simulated to frequency characteristics for inductance, quality-factor, SRF(Self- Resonance Frequency) using HFSS. The inductors without underpass and via have inductance of 1.11nH over the frequency range of 300 to 800 MHz, quality-factor of maximum 38 at 5 GHz, SRF of 18 GHz. Otherwise, inductors with underpass and via have inductance of 1.12nH over the frequency range of 300 to 800 MHz, quality-factor of maximum 35 at 5 GHz, SRF of 16 GHz.

• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.615-618
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• 2005

In this work, the effects of corner transistors in SOI MOSFETs were investigated. We fabricated SOI MOSFETs with various widths and a fixed length and characterized them. The SOI thickness was $4000{\AA}$ and the buried oxide(BOX) thickness was $4000{\AA}$. The isolation of active region was simply done by silicon etching and TEOS sidewall formation. Several undesirable characteristics have been reported for LOCOS isolation in fabrication on SOI wafers so far. Although we used an STI-like process instead of LOCOS, there were still a couple of abnormal phenomena such as kinks and double humps in drain current. Above all, we investigated the location of the parasitic transistors and found that they were at the corners of the SOI in width direction by high-resolution SEM inspection. It turned out that their characteristics are strongly dependent on the channel width. We made a contact pad through which we can control the body potential and figured out the dependency of operation on the body potential. The double humps became more prominent as the body bias went more negative until the full depletion of the channel where the threshold voltage shift did not occur any more. Through these works, we could get insights on the process that can reduce the effects of corner transistors in SOI MOSFETs, and several possible solutions are suggested at the end.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.62-62
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• 2015

In this study, we study the effects of CF4 plasma treatment on the characteristics of enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs). The CF4 plasma is generated by inductively coupled plasma reactive ion etching (ICP-RIE) system. The CF4 gas is decomposed into fluorine ions by ICP-RIE and then fluorine ions will effect the AlGaN/GaN interface to inhibit the electron transport of two dimension electron gas (2DEG) and increase channel resistance. The CF4 plasma method neither like the recessed type which have to utilize Cl2/BCl3 to etch semiconductor layer nor ion implantation needed high power to implant ions into semiconductor. Both of techniques will cause semiconductor damage. In the experiment, the CF4 treatment time are 0, 50, 100, 150, 200 and 250 seconds. It was found that the devices treated 100 seconds showed best electric performance. In order to prove fluorine ions existing and CF4 plasma treatment not etch epitaxial layer, the secondary ion mass spectrometer confirmed fluorine ions truly existing in the sample which treatment time 100 seconds. Moreover, transmission electron microscopy showed that the sample treated time 100 seconds did not have etch phenomena. Atomic layer deposition is used to grow Al2O3 with thickness 10, 20, 30 and 40 nm. In electrical measurement, the device that deposited 20-nm-thickness Al2O3 showed excellent current ability, the forward saturation current of 210 mA/mm, transconductance (gm) of 44.1 mS/mm and threshold voltage of 2.28 V, ION/IOFF reach to 108. As IV concerning the breakdown voltage measurement, all kinds of samples can reach to 1450 V.

• Journal of Sensor Science and Technology
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• v.14 no.1
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• pp.22-27
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• 2005

A thermoelectric flow sensor for small quantity of gas flow rate was fabricated using silicon wafer semiconductor process and bulk micromachining technology. Evanohm R alloy heater and chromel-constantan thermocouples were used as a generation heat unit and sensing parts, respectively. The heater and thermocouples are thermally isolated on the $Si_{3}N_{4}/SiO_{2}/Si_{3}N_{4}$ laminated membrane. The characteristics of this sensor were observed in the flow rate range from 0.2 slm to 1.0 slm and the heater power from 0.72 mW to 5.63 mW. The results showed that the sensitivities $(({\partial}({\Delta}V)/{\partial}(\dot{q}));{\;}{\Delta}V$ : voltage difference, $\dot{q}$ : flow rate) were increased in accordance with heater power rise and decreasing of flow rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.4 no.2
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• pp.297-305
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• 2000

It is observed that the initial properties and degradation characteristics on plasma of n/p-MOSFET with polycide and poly-Si as different gate materials under F-N stress and hot electron stress are affected by metal AR(Antenna Ratio) during plasma process. Compared to that of MOS devices with poly-Si gate material, reliability properties on plasma of MOS devices with polycide gate material are improved. This can be explained by that fluorine of tungsten polycide process diffuses through poly-Si into gate oxide and results in additional oxide thickness. The fact that MOS devices with polycide gate material can reduce damages of plasma process shows possibility that polycide gate material can be used as gate material for next generation MOS devices.