• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.423-426
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• 1998

Piezoresistive pressure sensors have fabricated using electrochemical etch-stop technique. Si diaphragm having thickness of n-epi. layer was fabricated and used to detect pressure range from 0 to 1 kg/$\textrm{cm}^2$. Piezoresistors were diffused 3${\times}$10$\^$18/ cm$\^$-3/ and placed at diaphragm edge for maximum pressure detection. The characteristics of electrochemical etch-stop in TMAH/lPA/pyrazine solution were also discussed. I-V curves of n and p-type Si in TMAH/lPA/pyrazine solution were obtained. Etching rate is highest at optimum etching condition, TMAH 25wt.%/IPA 17vo1.%/pyrazine 0.1/100m1, thus the elapsed time of etch-stop was reduced.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.557-560
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• 2000

Combination of SDB(Si-wafer Direct Bonding) and electrochemical etch-stop in TMAH anisotropic etchant can be used to create a variety of MEMS(Micro Electro Mechanical System). Especially, fabrication of SDB SOI structures using electrochemical etch-stop is accurate method to fabrication of 3D(three-dimensional) microstructures. This paper describes on the fabrication of SDB SOI structures with sealed cavity for MEMS applications and thickness control of active layer on the SDB SOI structure by electrochemical etch-stop. The flatness of fabricated SDB SOI structure is very uniform and can be improved by addition of TMAH to IPA and pyrazine.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.5
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• pp.431-436
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.741-744
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1890-1892
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• 2001

This paper described on the fabrication of microstructures by DRIE(Deep Reactive Ion Etching). SOI(Si-on-insulator) electric devices with buried cavities are fabricated by SDB technology and electrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -750 mm Hg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing(1000$^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated microstructures by DRIE as well as a accurate thickness control and a good flatness.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.124-124
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• 2010

Currently, extreme ultraviolet lithography (EUVL) is being investigated for next generation lithography. EUVL is one of competitive lithographic technologies for sub-22nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance due to the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore, new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1369-1371
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• 2001

This paper describes on thinning SDB SOI substrates by SDB technology and Electro-chemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic passivation potential. The surface roughness and selectively controlled thickness of the fabricated SOI substrates were analyzed by using AFM and SEM, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.397-400
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• 1997

This paper presentes the characteristics of Si anisotropic etching and electrochemical etch-stop in aqueous TMAH/IPA/pyrazine solution. (100) Si etching rate of 0.747 $\mu\textrm{m}$/min which faster 86% than TMAH 25 wt.%/IPA 17 vol.% solution was obtained using best etching condition at TMAH 25 wt.%/IPA 17 vol.%/pyrazine 0.1 g and the etching rate of (100) Si was decreased with more additive quantity of pyrazine. I-V curve of p-type Si in TMAH/IPA/pyrazine was obtained. OCP(Open Circuit Potential) and PP(Passivation Potential) were -2 V and -0.9 V, respectively. Si diaphragms were obtained by electrochemical etch-stop in aqueous TMAH/IPA/pyrazine solution.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.416-418
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• 1994

In this study, a silicon piezoresistive accelerometer is designed and fabricated using $p^+$ etch stop layer. The accelerometer consists of a seismic mass and tour cantilevers, and is fabricated mainly by the anisotropic etching method using EPW as an etchant. Eight piezoresistors are properly arranged and connected to make a bridge circuit so that acceleration in only one direction may be measured. The etch stop method is adequate to the mass-production and the precise thickness control of the diaphragms as well, whet compared with the electrochemecal etch stop method.