• Journal of Information Display
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• v.12 no.1
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• Korean Journal of Materials Research
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• v.5 no.2
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• pp.208-214
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• 1995

In order to study on the penetrations of HF solution acording to the geometrical shrinkage of contact-hole pattern size, the wet etch characteristics for oxide in microchannel patterns was investigated. Microchannel patterns of LPCVD oxide surrounded by nitride film, with dimensions of 0.1~1$\mu\textrm{m}$ height and 0.1~20$\mu\textrm{m}$, width, were fabricated. And the etch rates of oxide in HF solution were observed. It was found that oxide etch rate for micro-channel patterns in HF was not affected by pattern sizes and initial aspect ratios up to $0.1 \times 0.1 \mu \textrm{m}^{2} size and 1.2$\mu\textrm{m}$ depth. Finally, it was concluded that there were no special limitations for penetrations of HF solution in wet processes according to the geometrical shrinkage of contact-hole pattern size.

• Korean Journal of Metals and Materials
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• v.46 no.3
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• pp.169-173
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• 2008

Characteristics of etching and induced surface morphology variation by wet-etching of n-type GaN were investigated using phosphoric acidic solutions. Generally, the etch-rate was increased as the temperature of the etch solutions was increased, and the highest etch rate of about $300{\AA}/min$ was achieved at the temperature of $180^{\circ}C$. The morphology variation of the etched surface was observed by optical microscopy and atomic force microscopy. Initially, high density of hexagonal holes or pits were formed on the etched surface at the time of 40 min with the bimodal size of $20{\mu}m$ or $5{\mu}m$, respectively. However, as the etching time was increased further, the lateral size of the hexagonal holes or pits was increased, and finally, joined and merged together at the time of 100 min. This means that the etching of n-type GaN by phosphoric acidic solutions proceeded through the lateral widening and the merging of initial holes and pits.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.1
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• Journal of Magnetics
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• v.15 no.3
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• pp.132-137
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• 2010

Plasma etching of $SiO_2$ contact holes was statistically analyzed by a fractional factorial experimental design. The analysis revealed the dependence of the etch rate and DC self-bias voltage on the input factors of the magnetically enhanced reactive ion etching reactor, including gas pressure, magnetic field, and the gas flow rates of $CHF_3$, $CF_4$, and Ar. Empirical models of the DC self-bias voltage and etch rate were obtained. The DC self-bias voltage was found to be determined mainly by the operating pressure and the magnetic field, and the etch rate was related mainly to the pressure and the flow rates of Ar and $CHF_3$.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.136.2-136.2
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• 2015

반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1924-1926
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• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• Proceedings of the Materials Research Society of Korea Conference
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• 2009.05a
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• pp.50.2-50.2
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• 2009

사파이어는 질화물계 광전자소자 제작 시 박막 성장 기판으로 주로 사용되어 최근 그 중요성이 부각되고 있다. 특히 미세 패턴이 형성된 사파이어 기판을 이용하여 질화물계 발광다이오드 소자를 제작하면 빛의 난반사가 증가하여 광추출효율에 큰 개선이 나타난다. 또한 사파이어는 화학적 안정성이 뛰어나고, 높은 강도를 지녀 나노임프린트 등 여러 가지 패터닝 공정에서 패턴 형성 몰드로도 응용될 수 있다. 그러나 이와 같은 사파이어의 화학적 안정성으로 인하여 sub-micron 크기의 미세 패턴을 형성하기 힘들며, 현재 사파이어의 패턴은 micron 크기로 제한되어 사용되고 있다. 본 연구에서는 나노임프린트 리소그라피(NIL)를 사용하여 사파이어 웨이퍼의 c-plane위에 sub-micron 크기의 hole 패턴 및 pillar 패턴을 형성하였다. 우선 Hole 패턴을 형성하기 위해 사파이어 기판 위에 금속 hard mask 패턴을 UV 임프린트 공정과 etch 공정을 통해 형성하였다. 그리고 이 금속 패턴을 mask로 사파이어를 ICP 식각을 하여 hole 패턴을 형성하였다. 또한 Pillar 패턴을 형성하기 위해 lift-off 공정을 이용하여 금속 마스크 패턴을 형성하였고 이를 ICP 식각을 통해 사파이어 기판 위에 pillar 패턴을 형성하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.389-395
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• 2005

The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.