• Journal of Information Display
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• 제12권1호
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• pp.47-50
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• 2011

Highly stable amorphous indium.gallium.zinc-oxide (a-IGZO) thin-film transistors (TFTs) were fabricated with an etchstopper and via-hole structure. The TFTs exhibited 40 $cm^2$/V s field-effect mobility and a 0.21 V/dec gate voltage swing. Gate-bias stress induced a negligible threshold voltage shift (${\Delta}V_{th}$) at room temperature. The excellent stability is attribute to the via-hole and etch-stopper structure, in which, the source/drain metal contacts the active a-IGZO layer through two via holes (one on each side), resulting in minimized damage to the a-IGZO layer during the plasma etching of the source/drain metal. The comparison of the effects of the DC and AC stress on the performance of the TFTs at $60^{\circ}C$ showed that there was a smaller ${\Delta}V_{th}$ in the AC stress compared with the DC stress for the same effective stress time, indicating that the trappin of the carriers at the active layer-gate insulator interface was the dominant degradation mechanism.

• 한국재료학회지
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• 제5권2호
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• pp.208-214
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• 1995

콘택 홀 패턴의 미세화가 HF 용액의 침투에 미치는 영향을 파악하고자, 미세 채널 패턴에서의 산화막 습식 식각 특성을 조사하였다. LPCVD로 증착된 산화막을 두께 0.1~1$\mu\textrm{m}$, 선폭 0.1~20$\mu\textrm{m}$, 그리고 초기 깊이 ~1.2$\mu\textrm{m}$ 범위의 질화막으로 둘러 쌓인 미세 채널 패터으로 제작한 후, HF용액에 의한 산화막의 식각속도를 관찰하였다. 실험 결과로써, 크기가 $0.1 \times 0.1 \mu \textrm{m}^{2} 초기 깊이가 1.2$\mu\textrm{m}$인 고종횡비(~12)의 초미세 패턴에서도 식각 속도가 일정함을 볼 수 있어서, 콘택 홀 패턴의 미세화에 관계없이 반응액의 침투가 원활하게 이루어짐을 알 수 있었다.

• 대한금속재료학회지
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• 제46권3호
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• pp.169-173
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• 2008

본 논문에서는 인산을 이용하여을 인산을 이용하여 nGaN을 습식식각 할때의 표면식각 진행 특성을 조사 하였다. 인산을 이용한 고온에서의 식각은 diffusion rate limited regime을 통하여 이루어짐을 확인 하였으며, 또한 초기식각은 lateral 크기가 $20{\mu}m$에서 $5{\mu}m$ 정도인 bimodal 형태의 hexagonal 모양의 hole과 pits이 형성되며, 식각이 진행됨에 따라 표면에 형성된 hexagonal hole 등이 적층구조로 형성되거나 혹은 laterally 병합되며 식각됨을 관찰 하였다. 또한 PL 분석을 통하여 표면 거칠기 증가로 인한 extraction efficiency의 향상도 관찰할 수 있었다. 이러한 결과로부터 인산을 이용한 습식식각을 통하여 GaN의 표면 texturing 공정이 이용 가능할 수 있을 것으로 예상 된다.

• 전자공학회논문지A
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• 제30A권1호
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• pp.16-22
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• 1993

A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

• Journal of Magnetics
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• 제15권3호
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• pp.132-137
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• 2010

Plasma etching of $SiO_2$ contact holes was statistically analyzed by a fractional factorial experimental design. The analysis revealed the dependence of the etch rate and DC self-bias voltage on the input factors of the magnetically enhanced reactive ion etching reactor, including gas pressure, magnetic field, and the gas flow rates of $CHF_3$, $CF_4$, and Ar. Empirical models of the DC self-bias voltage and etch rate were obtained. The DC self-bias voltage was found to be determined mainly by the operating pressure and the magnetic field, and the etch rate was related mainly to the pressure and the flow rates of Ar and $CHF_3$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.136.2-136.2
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• 2015

반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1924-1926
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• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 춘계학술발표대회
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• pp.50.2-50.2
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• 2009

사파이어는 질화물계 광전자소자 제작 시 박막 성장 기판으로 주로 사용되어 최근 그 중요성이 부각되고 있다. 특히 미세 패턴이 형성된 사파이어 기판을 이용하여 질화물계 발광다이오드 소자를 제작하면 빛의 난반사가 증가하여 광추출효율에 큰 개선이 나타난다. 또한 사파이어는 화학적 안정성이 뛰어나고, 높은 강도를 지녀 나노임프린트 등 여러 가지 패터닝 공정에서 패턴 형성 몰드로도 응용될 수 있다. 그러나 이와 같은 사파이어의 화학적 안정성으로 인하여 sub-micron 크기의 미세 패턴을 형성하기 힘들며, 현재 사파이어의 패턴은 micron 크기로 제한되어 사용되고 있다. 본 연구에서는 나노임프린트 리소그라피(NIL)를 사용하여 사파이어 웨이퍼의 c-plane위에 sub-micron 크기의 hole 패턴 및 pillar 패턴을 형성하였다. 우선 Hole 패턴을 형성하기 위해 사파이어 기판 위에 금속 hard mask 패턴을 UV 임프린트 공정과 etch 공정을 통해 형성하였다. 그리고 이 금속 패턴을 mask로 사파이어를 ICP 식각을 하여 hole 패턴을 형성하였다. 또한 Pillar 패턴을 형성하기 위해 lift-off 공정을 이용하여 금속 마스크 패턴을 형성하였고 이를 ICP 식각을 통해 사파이어 기판 위에 pillar 패턴을 형성하였다.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.389-395
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• 2005

The etching technology of the high aspect ratio contact(HARC) is necessary at the critical contact processes of semiconductor devices. Etching the $SiO_{2}$ contact hole with the sub-micron design rule in manufacturing VLSI devices, the unexpected phenomenon of 'profile tilting' or 'bottom distortion' is often observed. This makes a short circuit between neighboring contact holes, which causes to drop seriously the device yield. As the aspect ratio of contact holes increases, the high C/F ratio gases, $C_{4}F_{6}$, $C_{4}F_{8}$ and $C_{5}F_{8}$, become widely used in order to minimize the mask layer loss during the etching process. These gases provide abundant fluorocarbon polymer as well as high selectivity to the mask layer, and the polymer with high sticking yield accumulates at the top-wall of the contact hole. During the etch process, many electrons are accumulated around the asymmetric hole mouth to distort the electric field, and this distorts the ion trajectory arriving at the hole bottom. These ions with the distorted trajectory induce the deformation of the hole bottom, which is called 'profile tilting' or 'bottom distortion'. To prevent this phenomenon, three methods are suggested here. 1) Using lower C/F ratio gases, $CF_{4}$ or $C_{3}F_{8}$, the amount of the Polymer at the hole mouth is reduced to minimize the asymmetry of the hole top. 2) The number of the neighboring holes with equal distance is maximized to get the more symmetry of the oxygen distribution around the hole. 3) The dual frequency plasma source is used to release the excessive charge build-up at the hole mouth. From the suggested methods, we have obtained the nearly circular hole bottom, which Implies that the ion trajectory Incident on the hole bottom is symmetry.

• 한국진공학회:학술대회논문집
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• 한국진공학회 1999년도 제17회 학술발표회 논문개요집
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.