• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12C
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• pp.1014-1020
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• 2008

Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.112-117
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• 2020

NAND flash memory is a non-volatile memory that retains stored data even without power supply. Internal memory used as a data storage device and solid-state drive (SSD) is used in portable devices such as smartphones and digital cameras. However, NAND flash memory carries the risk of electric shock, which can cause errors during read/write operations, so use error correction codes to ensure reliability. It efficiently recovers bad block information, which is a defect in NAND flash memory. BBT (Bad Block Table) is configured to manage data to increase stability, and as a result of experimenting with the error correction code algorithm, the bit error rate per page unit of 4Mbytes memory was on average 0ppm, and 100ppm without error correction code. Through the error correction code algorithm, data stability and reliability can be improved.

• Bulletin of the Korean Mathematical Society
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• v.57 no.2
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• pp.295-309
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• 2020

Loop transversal codes take an alternative approach to the theory of error-correcting codes, placing emphasis on the set of errors that are to be corrected. Hitherto, the loop transversal code method has been restricted to linear codes. The goal of the current paper is to extend the conceptual framework of loop transversal codes to admit nonlinear codes. We present a natural example of this nonlinearity among perfect single-error correcting codes that exhibit efficient domination in a circulant graph, and contrast it with linear codes in a similar context.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.426-433
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• 2006

In this paper, we propose an incremental redundancy(IR)-hybrid ARQ(HARQ) scheme which uses double binary turbo codes for error correction. We also propose a methodology for basic analysis of the throughput which is a performance index of HARQ. The proposed double binary turbo IR-HARQ scheme provides higher throughput than binary IR-HARQ, which uses binary turbo codes for error correction, at all $E_s/N_0$. An extra coding gain is also attained by using the proposed HARQ scheme over the coding gain achieved by turbo codes only.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.11a
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• pp.241-243
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• 2020

The high computational complexity of deep learning algorithms has led to the development of specialized hardware architectures. However, soft errors (bit flip) may occur in these hardware systems due to voltage variation and high energy particles. Many error correction methods have been proposed to counter this problem. In this work, we analyze an error correction mechanism based on repetition codes and an activation function. We test this method by injecting errors into weight filters and define an ideal error rate range in which the proposed method complements the accuracy of the model in the presence of error.

• ETRI Journal
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• v.45 no.3
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• pp.404-417
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• 2023

This paper proposed a novel method for constructing quasi-cyclic low-density parity-check (QC-LDPC) codes of medium to high code rates that can be applied in cloud data storage systems, requiring better error correction capabilities. The novelty of this method lies in the construction of sparse base matrices, using a girth greater than 4 that can then be expanded with a lift factor to produce high code rate QC-LDPC codes. Investigations revealed that the proposed large-sized QC-LDPC codes with high code rates displayed low encoding complexities and provided a low bit error rate (BER) of 10^-10 at 3.5 dB E_b/N₀ than conventional LDPC codes, which showed a BER of 10^-7 at 3 dB E_b/N₀. Subsequently, implementation of the proposed QC-LDPC code in a softwaredefined radio, using the NI USRP 2920 hardware platform, was conducted. As a result, a BER of 10^-6 at 4.2 dB E_b/N₀ was achieved. Then, the performance of the proposed codes based on their encoding-decoding speeds and storage overhead was investigated when applied to a cloud data storage (GCP). Our results revealed that the proposed codes required much less time for encoding and decoding (of data files having a 10 MB size) and produced less storage overhead than the conventional LDPC and Reed-Solomon codes.

• Honam Mathematical Journal
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• v.30 no.1
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• pp.33-45
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• 2008

Lee weight is more appropriate for some practical situations than Hamming weight as it takes into account magnitude of each digit of the word. In this paper, we obtain a sufficient condition over the number of parity check digits for codes correcting random errors and simultaneously detecting burst errors with Lee weight consideration.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.309-316
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• 1986

A concatenated coding system using a binary code as the inner code and a nonbinary code as the outer code has been constructed for the purpose of error correction. The complexity of a conventional coding system grows exponentially as the code length of a block code becomes longer. To reduce the complexity for ling code, an effective communication system has been proposed by cascading two codes-binary and norbinary codes. Using a parallel-to-serial circuit and a serial-to-parallel circuit, the concatenated coding system has been designed and constructed by empolying a (7,3) burst error correcting code as the inner code and a (7,3) Reed-Solomon code as the outer code. This system has been simulated and tested using a micro-computer. For the (49,9) concatenated coding system, the error probability of the channel has been evaluated and compared to different coding systems.