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Performance Analysis of Various Coding Schemes for Storage Systems  

Kim, Hyung-June (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실)
Kim, Sung-Rae (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실)
Shin, Dong-Joon (한양대학교 전자컴퓨터통신공학과 부호 및 통신 연구실)
Abstract
Storage devices such as memories are widely used in various electronic products. They require high-density memory and currently the data has been stored in multi-level format, that results in high error rate. In this paper, we apply error correction schemes that are widely used in communication system to the storage devices for satisfying low bit error rate and high code rate. In A WGN channel with average BER $10^{-5}$ and $5{\times}10^{-6}$, we study error correction schemes for 4-1evel cell to achieve target code rate 0.99 and target BER $10^{-11}$ and $10^{-13}$, respectively. Since block codes may perform better than the concatenated codes for high code rate, and it is important to use less degraded inner code even when many bits are punctured. The performance of concatenated codes using general feedforward systematic convolutional codes are worse than the block code only scheme. The simulation results show that RSC codes must be used as inner codes to achieve good performance of punctured convolutional codes for high code rate.
Keywords
BCH codes; Concatenated codes; Convolutional codes; Error-correcting codes; Storage system;
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  • Reference
1 B. Polianskikh and Z. Zilic, "Induced Error-Correcting Code for 2bit-per-cell Multi-Level DRAM," Circuits and Systems,.MWSCAS 2001, pp.352-355.
2 J. P. Odenwalder, Error Control Coding Handbook, Linkabit Corporation, San Diego, Calif., July 15, 1976.
3 M. Kim, "On Systematic Punctured Convolutional Codes," IEEE Trans. On Commun., Vol.45, No.2, pp.133-139, Feb. 1997.   DOI   ScienceOn
4 T. K. Moon, Error Correction Coding, Wiley, 2005.
5 S. Lin, and D. J. Costello, Error Control Coding, 2nd ed. Prentice Hall, Upper Saddle River, N.J., 2004.
6 G. D. Forney, Jr., Concatenated Codes, MIT Press, Cambridge, 1966.
7 김형준, 김성래, 신동준, "저장 장치를 위한 연접 부호화 기법의 성능 분석", 제18회 통신 정보 합동학술대회(JCCI'08), 2008년 4월.
8 T. Tanzawa, T. Tanaka, K Takeuchi, R Shirota, S.Aritome, H. Watanabe, G. Hemink, K. Shimizu, S. Sato,Y. Takeuchi, and K. Ohuchi, "A Compact On-Chip ECC for Low Cost Flash Memories," IEEE Journal of Solid State Circuit, Vol.32, No.5, pp.662-669, May 1997.   DOI   ScienceOn
9 M. Tuchler, and A. Dholakia, "Rate-(N− 1)/N Convolutional Codes with Optimal Spectrum," IBM Research Report RZ 3409 (# 93559) 06/28/02.
10 C. Berrou, A. Glavieux, and P. Thitimajshima, "Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes," IEEE ICC'93, pp.1064-1070, May 1993.