• Korean Journal of Materials Research
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• v.20 no.12
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• pp.645-648
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• 2010

The structure and morphology of epitaxial layer defects in epitaxial Si wafers produced by the Czochralski method were studied using focused ion beam (FIB) milling, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Epitaxial growth was carried out in a horizontal reactor at atmospheric pressure. The p-type Si wafers were loaded into the reactor at about $800^{\circ}C$ and heated to about $1150^{\circ}C$ in $H_2$. An epitaxial layer with a thickness of $4{\mu}m$ was grown at a temperature of 1080-$1100^{\circ}C$. Octahedral void defects, the inner walls of which were covered with a 2-4 nm-thick oxide, were surrounded mainly by $\{111\}$ planes. The formation of octahedral void defects was closely related to the agglomeration of vacancies during the growth process. Cross-sectional TEM observation suggests that the carbon impurities might possibly be related to the formation of oxide defects, considering that some kinds of carbon impurities remain on the Si surface during oxidation. In addition, carbon and oxygen impurities might play a crucial role in the formation of void defects during growth of the epitaxial layer.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• Current Photovoltaic Research
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• v.2 no.1
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• pp.1-7
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• 2014

We developed a method of growing thin Si film at $600^{\circ}C$ by hot wire CVD using a very thin large-grained poly-Si seed layer for thin-film Si solar cells. The seed layer was prepared by crystallizing an amorphous Si film by vapor-induced crystallization using $AlCl_3$ vapor. The average grain size of the p-type epitaxial Si layer was about $20{\mu}m$ and crystallographic defects in the epitaxial layer were mainly low-angle grain boundaries and coincident-site lattice boundaries, which are special boundaries with less electrical activity. Moreover, with a decreasing in-situ boron doping time, the mis-orientation angle between grain boundaries and in-grain defects in epitaxial Si decreased. Due to fewer defects, the epitaxial Si film was high quality evidenced from Raman and TEM analysis. The highest mobility of $360cm^2/V{\cdot}s$ was achieved by decreasing the in-situ boron doping time. The performance of our preliminary thin-film solar cells with a single-side HIT structure and $CoSi_2$ back contact was poor. However, the result showed that the epitaxial Si film has considerable potential for improved performance with a reduced boron doping concentration.

• Journal of the Korean Society for Heat Treatment
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• v.22 no.6
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• pp.354-360
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• 2009

This paper reports the oxidation mechanism of epitaxial Ni thin films grown on GaN/sapphire(0001) substrates, investigated by real-time x-ray diffraction and scanning electron microscopy. At the initial stage of oxidation process, a thin NiO layer with a thickness of ${\sim}50\;{\AA}$ was formed on top of the Ni films. The growth of such NiO layer was saturated and then served as a passive oxide layer for the further oxidation process. For the second oxidation stage, host Ni atoms diffused out to the surfaces of initially formed NiO layer through the defects running vertically to form NiO grains, while the sites that were occupied by host Ni, became voids. The crystallographic properties of resultant NiO films, such as grain size and mosaic distribution, rely highly on the oxidation temperatures.

• Ceramist
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• v.16 no.4
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• pp.37-44
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• 2013

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.285-288
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• 2004

탄화규소 기판의 에피 박막결함으로는 dislocation, micropipe, pin-hole 및 에피층 표면의 여러 가지 결함들이 있다. 이러한 결함들이 탄화규소 쇼트키 다이오드의 항복전압과 어떠한 상관관계가 존재하는지 알아 보기 위해 탄화규소 쇼트키 다이오드를 제작하고, 제작된 소자의 항복전압을 측정하였다. 에피 박막내의 결함 분포를 알아보기 위해 항복전압 측정후 KOH 용액을 이용한 SiC의 에칭을 수행하였으며, 제작된 여러소자들에 대해 항복전압의 분포도와 결함 분포도를 작성, 비교 관찰하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.5
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• pp.497-501
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• 2004

The crystal structure of the GaN film on the AIN buffer layer grown by R. F sputtering with different thickness has been studied using X-ray scattering and transmission electron microscopy(TEM). The interface roughness between the AIN buffer layer and the epitaxial GaN film, due to crossover from planar to island grains, produced edge dislocations. The strain, coming from lattice mismatch between the AIN buffer layer and the epitaxial GaN film, produced screw dislocations. The density of the edge and screw dislocation propagating from the interface between the GaN film and the AIN buffer layer affected the electric resistance of GaN film.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.916-923
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• 2004

In this paper, the strained Si$_{0.9}$Ge$_{0.1}$ epitaxial layers grown by a reduced pressure chemical vapor deposition (RPCVD) on Si (100) were characterized by Rutherford backscattering spectrometery (RBS) for the fabrication of an SiGe heterojunction bipolar transistor(HBT). RBS spectra of the ${Si}_0.9{Ge}_0.1$epitaxial layers grown on the Si substrates which were implanted with the phosphorus (P) ion and annealed at a temperature between $850^{\circ}C$ - $1000^{\circ}C$ for 30min were analyzed to investigate the post thermal annealing effect on the grown${Si}_0.9{Ge}_0.1$epitaxial layer quality. Although a damage of the substrates by P ion-implantation might be cause of the increase of RBS yield ratios, but any defects such as dislocation or stacking fault in the grown ${Si}_0.9{Ge}_0.1$ epitaxial layer were not found in transmission electron microscope (TEM) photographs. The post high temperature rapid thermal annealing (RTA) effects on the crystalline quality of the ${Si}_0.9{Ge}_0.1$ epitaxial layers were also analyzed by RBS. The changes in the RBS yield ratios were negligible for RTA a temperature between $900^{\circ}C$ - $1000^{\circ}C$for 20 sec, or $950^{\circ}C$for 20 sec - 60 sec. A SiGe HBT array shows a good Gummel characteristics with post RTA at $950^{\circ}C$ for 20 sec.sec.sec.

• Journal of the Korean institute of surface engineering
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• v.28 no.3
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• pp.174-181
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• 1995

Multilayered silicon cantilever beams as interconnection systems for bare chip burn-in socket applications have been designed, fabricated and characterized. Fabrication processes of the beam are employing standard semiconductor processes such as thin film processes and epitaxial layer growth and silicon wet etching techniques. We investigated silicon etch rate in 1-3-10 etchant as functions of doping concentration, surface mechanical stress and crystal defects. The experimental results indicate that silicon etch rate in 1-3-10 etchant is strong functions of doping concentration and crystal defect density rather than surface mechanical stress. We suggested the new fabrication processes of multilayered silicon cantilever beams.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.111-115
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• 2024

Silicon carbide (SiC) has emerged as a promising material for next-generation power semiconductor materials, due to its high thermal conductivity and high critical electric field (~3 MV/cm) with a wide bandgap of 3.3 eV. This permits SiC devices to operate at lower on-resistance and higher breakdown voltage. However, to improve device performance, advanced research is still needed to reduce point defects in the SiC epitaxial layer. This work investigated the electrical characteristics and defect properties using DLTS analysis. Four deep level defects generated by the implantation process and during epitaxial layer growth were detected. Trap parameters such as energy level, capture-cross section, trap density were obtained from an Arrhenius plot. To investigate the impact of defects on the device, a 2D TCAD simulation was conducted using the same device structure, and the extracted defect parameters were added to confirm electrical characteristics. The degradation of device performance such as an increase in on-resistance by adding trap parameters was confirmed.