• 한국산업융합학회 논문집
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• 제4권4호
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• pp.451-455
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• 2001

The epitaxial growth of Ge on the clean and surfactant(Sn) adsorbed surface of Ge(111) was studied by the intensity oscillation of a RHEED specular spot. In the case of epitaxial growth without the adsorbed surfactant, the RHEED intensity oscillation was stable and periodic up to 24ML at the substrate temperature of $200^{\circ}C$. Therefore the optimum temperature for the epitaxial growth of Ge on clean Ge(111) seems to be $200^{\circ}C$. However, in the case of epitaxial growth with the adsorbed surfactant, the irregular oscillations are observed in the early stage of the growth. The RHEED intensity oscillation was very stable and periodic up to 38ML, and the $d2{\times}2$ structure was not charged with continued adsorption of Ge at the substrate temperature of $200^{\circ}C$. These results may be explained by the fact that the diffusion length of Ge atoms is increased by decreasing the activation energy of the Ge surface diffusion, resulted by segregation of Sn toward the growing surface. From the desorption process, the desorption energy of Sn in Ge $\sqrt{5}{\times}\sqrt{5}$ structure is observed to be 3.28eV.

• 한국재료학회지
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• 제13권2호
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• pp.88-93
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• 2003

Co/Ti bilayer structure in Co salicide process helps to the improvement of device speed by lowering contact resistance due to the epitaxial growth of $CoSi_2$layers. We investigated the epitaxial growth and interfacial mass transport of $CoSi_2$layers formed from $150 \AA$-Co/Ti structure with two step rapid thermal annealing (RTA). The thicknesses of Ti layers were varied from 20 $\AA$ to 100 $\AA$. After we confirmed the appropriate deposition of Ti film even below $100\AA$-thick, we investigated the cross sectional microstructure, surface roughness, eptiaxial growth, and mass transportation of$ CoSi_2$films formed from various Ti thickness with a cross sectional transmission electron microscopy XTEM), scanning probe microscopy (SPM), X-ray diffractometery (XRD), and Auger electron depth profiling, respectively. We found that all Ti interlayer led to$ CoSi_2$epitaxial growth, while $20 \AA$-thick Ti caused imperfect epitaxy. Ti interlayer also caused Co-Ti-Si compounds on top of $CoSi_2$, which were very hard to remove selectively. Our result implied that we need to employ appropriate Ti thickness to enhance the epitaxial growth as well as to lessen Co-Ti-Si compound formation.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.344-349
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• 2006

A sublimation epitaxial method, referred to as the Closed Space Technique (CST) was adopted to produce thick SiC epitaxial layers for power device applications. We aimed to systematically investigate the dependence of SiC epilayer quality and growth rate during the sublimation growth using the CST method on various process parameters such as the growth temperature and working pressure. The etched surface of a SiC epitaxial layer grown with low growth rate $(30{\mu}m/h)$ exhibited low etch pit density (EPD) of ${\sim}2000/cm^2$ and a low micropipe density (MPD) of $2/cm^2$. The etched surface of a SiC epitaxial layer grown with high growth rate (above $100{\mu}m/h$) contained a high EPD of ${\sim}3500/cm^2$ and a high MPD of ${\sim}500/cm^2$, which indicates that high growth rate aids the formation of dislocations and micropipes in the epitaxial layer. We also investigated the Schottky barrier diode (SBD) characteristics including a carrier density and depletion layer for Ni/SiC structure and finally proposed a MESFET device fabricated by using selective epilayer process.

• 한국결정성장학회지
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• 제11권5호
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• pp.207-210
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• 2001

Metal-organic VPE (MOVPE) epitaxial growth procedure and related device fabrication technique are reported for GaInP-based epitaxial materials and devices. For GaInP/GaInAs two-dimensional electron-gas field-effect transistor (TEGFET), a promising epitaxial stacking structure resulting in enhanced electron mobility is given. In conjunction with this, a new device fabrication technique to improve luminous intensity of GaInP-based LED is also shown.

• 한국자기학회:학술대회 개요집
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• 한국자기학회 2009년도 정기총회 및 동계학술연구발표회
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• pp.190-190
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• 2009

We report the epitaxial growth of MgO and CoFe/MgO on Ge (001) substrates using molecular beam epitaxy. It was found that the epitaxial growth of a MgO film on Ge could be realized at a low growth temperature of $125{\pm}5^{\circ}C$ and the MgO matches the Ge with a cell ratio of $\sqrt{2}$:1 which renders MgO rotated by $45^{\circ}$ relative to Ge. In-situ and ex-situ structural characterizations reveal the epitaxial crystal growth of bcc CoFe/MgO on Ge with the in-plane crystallographic relationship of CoFe(001)[100] || MgO(001)[110] || Ge(001)[100], exhibiting sharp interfaces in the (001) matching planes. The saturation magnetization of the sample is $1430{\pm}20$ emu/cc, which is comparable to the value of bulk CoFe.

• Current Photovoltaic Research
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• 제1권2호
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• pp.103-108
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• 2013

Epitaxial growth of a high-quality thin Si film is essential for the application to low-cost thin-film Si solar cells. A polycrystalline Si film was grown on a $SiO_2$ substrate at $450^{\circ}C$ by a Al-assisted crystal growth process. For the purpose, a thin Al layer was deposited on the $SiO_2$ substrate for Al-assisted crystal growth. However, the epitaxial growth of Si film resulted in a rough surface with humps. Then, we introduced a thin amorphous Si seed layer on the Al film to minimize the initial roughness of Si film. With the help of the Si seed layer, the surface of the epitaxial Si film was smooth and the crystallinity of the Si film was much improved. The grain size of the $1.5-{\mu}m$-thick Si film was as large as 1 mm. The Al content in the Si film was 3.7% and the hole concentration was estimated to be $3{\times}10^{17}/cm^3$, which was one order of magnitude higher than desirable value for Si base layer. The results suggest that Al-doped Si layer could be use as a seed layer for additional epitaxial growth of intrinsic or boron-doped Si layer because the Al-doped Si layer has large grains.

• 한국재료학회지
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• 제20권12호
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• pp.645-648
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• 2010

The structure and morphology of epitaxial layer defects in epitaxial Si wafers produced by the Czochralski method were studied using focused ion beam (FIB) milling, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). Epitaxial growth was carried out in a horizontal reactor at atmospheric pressure. The p-type Si wafers were loaded into the reactor at about $800^{\circ}C$ and heated to about $1150^{\circ}C$ in $H_2$. An epitaxial layer with a thickness of $4{\mu}m$ was grown at a temperature of 1080-$1100^{\circ}C$. Octahedral void defects, the inner walls of which were covered with a 2-4 nm-thick oxide, were surrounded mainly by $\{111\}$ planes. The formation of octahedral void defects was closely related to the agglomeration of vacancies during the growth process. Cross-sectional TEM observation suggests that the carbon impurities might possibly be related to the formation of oxide defects, considering that some kinds of carbon impurities remain on the Si surface during oxidation. In addition, carbon and oxygen impurities might play a crucial role in the formation of void defects during growth of the epitaxial layer.

• 한국재료학회지
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• 제10권11호
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• pp.738-741
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• 2000

사이클로펜타디에닐 디카보닐 코발트 (Co(η(sup)5-C(sub)5H(sub)5) ($CO_2$)의 반응성 화학 기상 증착법에 의해 $600^{\circ}C$ 근처의기판온도에서 (100)Si 기판 위에 균일한 에피택셜 CoSi2 층이 후열처리를 거치지 않고 직접 성장되었다. (100) Si 기판 위에서 에피택셜 CoSi(sub)2 층의 성장 속도론을 $575^{\circ}C$에서 $650^{\circ}C$의 온도 구간에서 조사하였다. 증착 초기 단계에서 판(plate)모양의 CoSi(sub)2 스차이크가 쌍정의 구조를 가지고 (100) Si 기판에서 <111> 방향을 따라서 불연속적으로 핵생성되었다. {111}과 (100)면을 가진 불연속의 CoSi(sub)2 판은 (100) Si 위에서 평평한 계면으로 이루어진 에피택셜 층으로 성장했다. (100) Si 위에서 에피택셜 CoSi(sub)2 층을 통한 Co의 확산에 의해 제어되는 것으로 나타났다.

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1998년도 PROCEEDINGS OF THE 14TH KACG TECHNICAL MEETING AND THE 5TH KOREA-JAPAN EMGS (ELECTRONIC MATERIALS GROWTH SYMPOSIUM)
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• pp.173-176
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• 1998

Epitaxial Si layers were deposited on n- or p-type Si(100) substrates by hot-wall chemical vapor deposition (CVD) technique using the {{{{ {SiH }_{ 2} {Cl }_{2 } - {H }_{ 2} }}}}chemistry. Thermodynamic calculations if the Si-H-Cl system were carried out to predict the window of actual Si deposition procedd and to investigate the effects of process variables(i.e., the deposition temperature, the reactor pressure, and the source gas molar ratios) on the growth of epitaxial layers. The calculated optimum process conditions were applied to the actual growth runs, and the results were in good agreement with the calculation. The expermentally determined optimum process conditions were found to be the deposition temperature between 900 and 9$25^{\circ}C$, the reactor pressure between 2 and 5 Torr, and source gad molar ration({{{{ {H }_{2 }/ {SiH }_{ 2} {Cl }_{2 } }}}}) between 30 and 70, achieving high-quality epitaxial layers.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1357-1359
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• 2001

0.2${\mu}m$ 이하의 최소 선폭을 가지는 소자를 구현할 때 drain induced barrier lowering (DIBL)이나 hot electron effect와 같은 short channel effect (SCE)가 나타나며 이로 인하여 소자의 신뢰성이 악화되기도 한다. 이를 개선하기 위한 방법 중 하나가 silicon selective epitaxial growth (SEG)를 이용한 elevated source/drain (ESD) 구조이다. 본 연 구에서는 silicon selective epitaxial growth를 이용하여 elevated source/drain 구조를 갖는 MOSFET 소자와 일반적인 MOSFET 구조를 갖는 소자와의 차이를 elevated source/drain의 높이 변화에 따른 전류 전압 특성을 이용하여 비교, 분석하였으며 그 결과 elevated source/drain 구조가 short channel effect를 감소시킴을 확인할 수 있었다.