• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2003.02a
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• pp.287-290
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• 2003

For microwave device applications, c-axis oriented high temperature superconducting YBa$_2$Cu$_3$O$_{7-{\delta}}$ (HTS-YBCO) epitaxial thin films on the r-cut sapphire substrate(Al$_2$O$_3$) were prepared. In order to reduce the lattice mismatch with a substrate and to enhance the crystallity of HTS thin films, CeO$_2$ buffer layer on the r-cut sapphire substrate was grown by the RF-magnetron sputtering. The YBCO films on the CeO$_2$ buffer layer were deposited using the pulsed-laser deposition (PLD) method. These HTS YBCO /CeO$_2$/Al$_2$O$_3$ multilayer thin films(30 $\times$ 30 mm$^2$) routinely exhibited a critical temperature(T$_{c}$) of 89 K from the R-T measurement. Using HTS YBCO/CeO$_2$ /Al$_2$O$_3$ multilayer thin film. We fabricated and characterized the microwave passive devices (planar type filters) with cryopack-age such as the coupled -line type low-pass filter (LPF) and the open-loop meander type bandpass filter (BPF).filter (BPF).).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.66-72
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• 1995

Using the Si/SiGe layer grown by solid source molecular beam epitaxy(SSMBE) on the LOCOS-patterned wafers, an emitter-base self-aligned hterojunction biplar transistor(HBT) with the polysilicon-emitter and the silicon germanium(SiGe) base has been fabricated. Trech isolation process, planarization process using a chemical-mechanical poliching, and the selectively implanted collector(SIC) process were performed. A titanium disilicide (TiSi$_{2}$), as a base electrode, was used to reduce an extrinsic base resistance. To prevent the strain relaxation of the SiGe epitaxial layer, low temperature (820${^\circ}C$) annealing process was applied for the emitter-base junction formation and the dopant activation in the arsenic-implanted polysilicon. For the self-aligned Si/SiGe HBT of 0.9${\times}3.8{\mu}m^{2}$ emitter size, a cut-off requency (f$_{T}$) of 17GHz, a maximum oscillation frequency (f$_{max}$) of 10GHz, a current gian (h$_{FE}$) of 140, and an emitter-collector breakdown voltage (BV$_{CEO}$) of 3.2V have been typically achieved.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05a
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• pp.30-33
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• 2003

YBCO coated conductor, also called the 2nd generation high temperature superconducting wire, consists of oxide multi-layer hetero-epitaxial thin films. Pulsed laser deposition (PLD) is one of many film deposition methods used to make coated conductor, and is the one known to be the best to make superconducting layer so far. As a part of the effort to make long length coated conductor, the optimum deposition condition of YBCO film on single crystal substrate (SrTiO3) was investigated using PLD. Substrate temperature, oxygen partial pressure, and laser fluence were varied to find the best combination to grow high quality YBCO film.

• Journal of the Korean Magnetics Society
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• v.9 no.5
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• pp.256-262
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• 1999

Sputter deposited CoCr(Mo)/Si film were studied with emphasis on the correlation between magnetic properties and crystallographic orientation. The perpendicular coercivities of CoCr films decreased with Si underlayer thickness, whereas those of CoCrMo films increased with Si underlayer thickness. It has been explained that additions of the larger atomic radius Mo atoms in CoCr films impedes crystal growth resulting in a decrease in grain size, thus this small grain size may induce high perpendicular coercivity. The c-axis alignment of CoCrMo film was improved due to addition of 2at.%Mo. It means CoCrMo layer grow self-epitaxial directly from orientation and structure of Si underlayer when the main layer grow on underlayer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.180-183
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• 2003

The monolayer of oxygen atoms sandwitched between the adjacent nanocrystalline silicon layers was formed by ultra high vacuum-chemical vapor deposition (UHV-CVD). This multi-layer Si-O structure forms a new type of superlattice, semiconductor-atomic superattice (SAS). According to the experimental results, high-resolution cross-sectional transmission electron microscopy (HRTEM) shows epitaxial system. Also, the current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the system may form an epitaxially grown insulating layer as possible replacement of silicon-on-insulator (SOI), a scheme investigated as future generation of high efficient and high density CMOS on SOI.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.758-765
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• 1986

The design, fabrication and performance of vertical double diffused power MOSFET (VDMOS) were described. On the antimony (Sb) doped (~7x10**17 cm**-3) silicon substrate (N+), epitaxial layer(N-) was grown. The thickness and the resistivity of this layer were 32\ulcorner and about 12\ulcorner-cm, respectively. The P- channel length which was controlled by sequential P-/N+ double diffuison method was about 1~2 \ulcorner, and was processed with the self alignment of 21 \ulcorner width poly silicon. To improve the breakdown voltage with constant on-resistance (Ron) about 1\ulcorner, three P+ guard rings were laid out around main pattern. With chip size of 4800\ulcorner x4840 \ulcorner, the VDMOS has shown breakdown voltage of 410~440V, on-resistance within 1.0~1.2\ulcornerand the current capablity of more than 5A.

• ETRI Journal
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• v.26 no.6
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• pp.575-582
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• 2004

Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a $1.1\;{\mu}m^2$ 6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.187-194
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• 1998

InGaAsP epitaxial layers lattice matched to InP were grown at 600 and $620^{\circ}C$ by low pressure metalorganic chemical vapor deposition. Solid phase composition of group III was controlled by the diffusion flux gas phase to the reachion surface. For the case of group V, the difference of As and P vapor pressure and pyrolysis efficiency of $PH_3$and $AsH_3$ mainly determined their in corporation into solid. An abnormal behavior of peak energy shift was observed below 75K in temperature variant photoluminescence study. This abnormal behavior was explained by the difference in order of ordering which makes spatial variation of energy gap in InGaAsP layer and this explanation was supported by the analyses of transmission electron microscopy and transmission spectroscopy.

• Korean Journal of Optics and Photonics
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• v.18 no.2
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• pp.155-161
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• 2007

A new and simple method of 3-dimensional circuit modeling and analysis is proposed and verified experimentally for the first time by determining 3-dimensional current flow and 2-dimensional light distribution in blue InGaN/GaN multi-quantum well (MQW) light emitting diode (LED) devices. Circuit parameters of the LED consist of the resistance of the metallic film and epitaxial layer, and the intrinsic diode which represents the active region emitting the light. The circuit parameters are extracted from the transmission line model (TLM) and current-voltage relation. We applied the >> proposed method and extracted circuit parameters to obtain the light emission pattern in a top-surface emitting-type LED. The current spreading effect is analyzed theoretically and quantitatively with a variation of the resistance of metallic and epitaxial layers. The emitting-light distribution of the fabricated blue LED showed a good agreement with the analyzed result, which shows the dark emission intensity at the corner of the p-electrode.

• Journal of Sensor Science and Technology
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• v.14 no.2
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• pp.96-100
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• 2005

The planar Schottky diodes were fabricated and modeled to probe the device applicability of the cracked GaN epitaxial layer on a (111) silicon substrate. On the unintentionally n-doped GaN grown on silicon, we deposited Ti/Al/Ni/Au as the ohmic metal and Pt as the Schottky metal. The ohmic contact achieved a minimum contact resistivity of $5.51{\times}10.5{\Omega}{\cdot}cm^{2}$ after annealing in an $N_{2}$ ambient at $700^{\circ}C$ for 30 sec. The fabricated Schottky diode exhibited the barrier height of 0.7 eV and the ideality factor was 2.4, which are significantly lower than those parameters of crack free one. But in photoresponse measurement, the diode showed the peak responsivity of 0.097 A/W at 300 nm, the cutoff at 360 nm, and UV/visible rejection ratio of about $10^{2}$. The SPICE(Simulation Program with Integrated Circuit Emphasis) simulation with a proposed model, which was composed with one Pt/GaN diode and three parasitic diodes, showed good agreement with the experiment.