• The Transactions of the Korea Information Processing Society
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• v.1 no.4
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• pp.517-530
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• 1994

In this paper, design of small microprocessor unit is implemented using research purpose VHDL and CAD tools by top-down design method. For this, original basic MPU and its pipelining architectures are suggested. Once, design target, instruction sets, architecture are decided, the operation is confirmed by C language simulation, and then the operation is confirmed by checking internal register contents for given inputs in the case of VHDL simulation. Then, design layouts are made by full/semi-custom design methods by research CAD tools and related simulation is implemented. The feasibility of suggested pipelined structure for performance improvement is confirmed by simulation, and related problems and future research directions are discussed. In conclusion, the MPU design methodology is set up and the design change of architecture is possible by this paper.

• ETRI Journal
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• v.35 no.5
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.1003-1006
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• 2005

Vertex shader of GPU in personal computer is advanced in functions as to be half of traditional fixed T&L functions. And, capacity of memory for saving resources to process instructions is unlimited. GPU that can be programmed by programmer is needed for mobile system as well as personal computer. In this paper, we implement software virtual machine for vertex shader using C++ Language. Our goal is designing hardware GPU that can apply to mobile system. The virtual machine consists of nVidia GPU instructions. Input Data to virtual machine is generated by Microsoft fxc compiler. That is to say, Input Data is compiled shader program written in HLSL, Cg, or ASM. The virtual machine will be a reference model for designing hardware GPU and can be used for Testbed to test added or modified instruction.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1777-1780
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• 2005

OFDM(Orthogonal Frequency Division Multiplexing)은 제 4 세대 기술로 일컬어지는 변조 방식으로 최근 유럽의 디지털 오디오 방송(DAB)과 디지털 비디오 방송(DVB)에 표준으로 사용되고 있으며, IEEE 802.11a 무선 LAN 및 디지털 가입자라인 xDSL 에서도 사용되고 있다. 본 논문에서는 OFDM 모뎀 구현의 핵심이라고 할 수 있는 64-포인트 FFT(Fast Fourier Transform) 프로세서의 여러 가지 구조를 분석하고, 이들과 비교하여 성능 대 면적 비를 획기적으로 향상시킨 새로운 FFT 프로세서인 Radix-4,2 SIC (Single Instruction Computer) 구조를 제안하였다. 본 논문에서 제안하는 SIC 구조는 버터플라이 연산의 재사용을 극대화하였으며 Radix-4,2 알고리즘을 사용함으로써 FFT 프로세서에서 면적의 80%를 차지하는 복소곱셈기의 수를 감소시켜 크기를 획기적으로 줄인 결과를 보여 준다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1681-1684
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• 2004

90 년대 후반부터 웹 기반 수업(Web-based instruction)이라 하여 인터넷을 이용한 새로운 교육방법이 시도되었다. WBI에 필요한 각종 프로그래밍을 수작업으로 진행하여야 한다는 문제점을 극복하기 위해 개발된 학습운영체제(Learning Management System)가 개발되면서 인터넷을 통한 교육은 급속히 확산되고 있다. 무선 인터넷 기술까지 수용하는 개념인 소위 e-Learning 체제로 발전되면서 e-Learning의 수요는 급속히 증가하게 되었다. e-Learning 기술 표준 개발을 실질적으로 주도하는 기관들인 IEEE, AICC, IMS가 제안하는 개별 표준안들을 ADL에서 SCORM(Sharable Content Object Reference Model)이라는 종합적인 표준안으로 수렴하게 되면서 SCORM을 기준으로 만든 다양한 컨텐츠가 개발되고있다.

• Structural Monitoring and Maintenance
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• v.1 no.3
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• pp.293-308
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• 2014

In the aeronautical environment, numerous regulatory and communication protocols exist that cover interconnection of on-board equipment inside the aircraft. Developed and implemented by the airlines since the 1960s, these communication systems are reliable, strong, certified and able to contact different sensors distributed throughout the aircraft. However, the scenario is slightly different in the structural health monitoring (SHM) field as the requirements and specifications that a global SHM communication system must fulfill are distinct. The number of SHM sensors installed in the aircraft rises into the thousands, and it is impossible to maintain all of the SHM sensors in operation simultaneously because the overall power consumption would be of thousands of Watts. This design of a new communication system must consider aspects as management of the electrical power supply, topology of the network for thousands of nodes, sampling frequency for SHM analysis, data rates, selected real-time considerations, and total cable weight. The goal of the research presented in this paper is to describe and present a possible integration scheme for the large number of SHM sensors installed on-board an aircraft with low power consumption. This paper presents a new communications system for SHM sensors known as the Bi-Instruction Link Bi-Operator (BILBO).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.77-86
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• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.3
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• pp.145-154
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• 2007

Dynamic update of kernel can change kernel functionality and fix bugs in runtime. Dynamic update is important because it leverages availability, reliability and flexibility of kernel. An instruction-granularity update technique has been used for dynamic update. However, it is difficult to apply update technique for a commodity operating system kernel because development and maintenance of update code must be performed with assembly language. To overcome this difficulty, we design the function-granularity dynamic update system which uses high-level language such as C language. The proposed update system makes the development and execution of update convenient by providing the development environment for update code which is same for kernel development. We implement this system for Linux and demonstrate an example of update for do_coredump() function which is reported it has a vulnerable point for security. The update was successfully executed.

• Journal of IKEEE
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• v.11 no.4
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• pp.358-363
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• 2007

This paper presents a floating point unit(FPU) with 3 stages for a 3D graphics shader engine. It targeted to accelerate 3D graphics in portable device environments. In order to design a balanced architecture for a shader engine, we analyzed shader assembly instructions and estimated the performance of FPU with the method we propose. The proposed unit handles 4-dimensional data through separated two paths that are lead to general operation module and special function module. The proposed FPU is compiled as a form of the cascade FPU with 3 stages to efficiently handle a matrix operation with relatively low hardware overhead. Except some complex instructions that are executed using macro instructions, all instructions complete an operation in a single instruction cycle at 100MHz frequency. A special function module performs all operations in a single clock cycle using the Newton Raphson method with the look-up table.

• Journal of Electrical Engineering and information Science
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• v.2 no.4
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• pp.1-7
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• 1997

A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains tow IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. the IU is a 32-bit scalar processor expecially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. ETH SMPC is implemented in VLSI circuit by custom design and automated design tools.