• 마이크로전자및패키징학회지
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• 제25권1호
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• pp.17-22
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• 2018

본 논문에서는 임베딩 패키지의 솔더 조인트 신뢰성에 미치는 솔더 조인트의 에이징 효과를 유한요소법에 의한 수치해석을 통해 연구하였다. SAC305 솔더 조인트의 에이징 시간은 0, 60, 180 일이 적용되었고 신뢰성 분석을 위해 패키지 휨, ECS(Equivalent Creep Strain) 및 TSED(Total Strain Energy Density)이 분석되었다. 연구결과에 따르면 임베딩 패키지의 휨이 비임베딩 패키지에 비해 감소하여 임베딩 패키지내 솔더 접합부의 신뢰성이 높을 것으로 예측되었다. 또한, 에이징 시간이 길수록 임베디드 패키지의 휨이 감소하지만 솔더 조인트의 신뢰성 수명도 감소할 것으로 분석되었다.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.277-278
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• 2012

• 한국공작기계학회논문집
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• 제16권6호
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• pp.201-204
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• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.

• 대한전자공학회논문지TC
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• 제41권8호
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• pp.19-26
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• 2004

패키지는 전기적인 특성에 있어서 우수한 고주파 전송 특성을 지녀야한다. 그러나 집적회로면이 위로 향하는 세라믹 패키지(Face-up Package)는 본드와이어 연결 시 고주파의 기생 특성이 크게 증가하여 시스템 전체의 성능에 큰 제한을 가져온다. 본 논문에서는 향상된 정합특성을 갖는 새로운 밀리미터파 세라믹 패키지 급전구조를 제안하였고, 유한요소법(FEM: Finite Element Method)을 이용하여 20 ∼ 50 GHz에서 해석 및 설계를 하고 제작하였다. 측정 결과, 삽입된 금속판 (Embedded Metal Sheet)을 가지는 세라믹 패키지 급전구조는 47GHz까지 기존의 세라믹 패키지보다 0.85dB 그리고 본드와이어 부분에 일반적인 에폭시( ε/sub γ/ = 4)를 사용하여 몰딩한 세라믹 패키지보다 0.4dB가 개선된 삽입손실의 특성을 얻을 수 있었다. 따라서 본 해석결과는 소형의 세라믹 패키지 및 MMIC(Monolithic Microwave Integrated Circuit) 모듈 개발에 효과적으로 활용될 수 있으리라 기대된다.

• 센서학회지
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• 제31권1호
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.1504-1505
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• 2007

In this paper, fully embedded high Dk BTO MIM capacitors have been developed into a multi-layered organic package substrate for low cost RF SOP (System on Package) applications. These embedded MIM capacitors were designed and simulated by using CST 3D EM simulators for finding out optimal geometries and verifying their applicability. The embedded MIM capacitor with a size of $550\;{\times}\;550\;um^2$ has a capacitance of 5.3pF and quality factor of 43 at 1.5 GHz, respectively. The measured performance characteristics were well matched with 3D EM simulated ones. Equivalent circuit parameters of the embedded capacitors were extracted for making a design library.

• 마이크로전자및패키징학회지
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• 제15권1호
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• pp.39-44
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• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.109-119
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• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.262-263
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• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• 광학세계
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• 통권117호
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• pp.23-25
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• 2008

RF embedded 기판의 기술은 Module과 Package라는 응용 제품을 거치면서 최종적으로는 기존의 여러 가지 제품의 Mother Board(특히 휴대폰)에 접목 시키기 위한 노력이 계속 진행되고 있다. 업계 및 Research 기관의 조사 결과에 따르면 PCB 시장의 성장세와 맞물려 Embedded 시장규모는 큰 폭의 상승이 예상된다. 본 고에서는 높은 유전율을 가지는 강유전체 물질의 Embedded capacitor 적용을 위해 레이저 기술을 전자부품 제조현장에 적용하는 연구의 진행상황을 소개하고자 한다.