• Journal of the Microelectronics and Packaging Society
• /
• v.25 no.1
• /
• pp.17-22
• /
• 2018

In this paper, the effects of solder joint aging on the reliability of embedded package solder joints were investigated using numerical analysis by finite element method. Solder joints were SAC305 with aging time 0, 60, 180 days. For reliability analysis, warpage of package and equivalent creep strain (ECS) and total strain energy density (TSED) of solder joint were analyzed. The analysis results show that the package warpage is decreased in the case of the embedded package compared to the non embedded package, and the reliability life of the solder joint is predicted to be high. Also, it was interpreted that the longer the aging time, the less the warpage of the embedded package, but the reliability life of the solder joint would be shortened.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2012.10a
• /
• pp.277-278
• /
• 2012

• Transactions of the Korean Society of Machine Tool Engineers
• /
• v.16 no.6
• /
• pp.201-204
• /
• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.8
• /
• pp.19-26
• /
• 2004

High performance packages must provide excellent transmission characteristics. In face-up ceramic packages, however, parasitic characteristics of bondwires are not negligible at millimeter-wave frequencies. Consequently, the electrical performance of ceramic packages is degraded. In をis paper, we propose a new millimeter-wave ceramic package feed-through having Embedded Metal Sheets (EMS). The package that contains double-bondwire interconnections is analyzed by the FEM (Finite Element Method) and measured from 20 to 50GHz. As a result, the proposed package having Embedded Metal Sheets (EMS) achieved 0.85dB, 0.4dB insertion loss improvement on the conventional and the double bondwires buried in epoxy ( $\varepsilon_{{\gamma}}$/ = 4) ceramic package respectively to 47GHz. This improved ceramic package will be useful for MMICs modules and small ceramic packages developments.amic packages developments.

• Journal of Sensor Science and Technology
• /
• v.31 no.1
• /
• pp.36-40
• /
• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.1504-1505
• /
• 2007

In this paper, fully embedded high Dk BTO MIM capacitors have been developed into a multi-layered organic package substrate for low cost RF SOP (System on Package) applications. These embedded MIM capacitors were designed and simulated by using CST 3D EM simulators for finding out optimal geometries and verifying their applicability. The embedded MIM capacitor with a size of $550\;{\times}\;550\;um^2$ has a capacitance of 5.3pF and quality factor of 43 at 1.5 GHz, respectively. The measured performance characteristics were well matched with 3D EM simulated ones. Equivalent circuit parameters of the embedded capacitors were extracted for making a design library.

• Journal of the Microelectronics and Packaging Society
• /
• v.15 no.1
• /
• pp.39-44
• /
• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.09a
• /
• pp.109-119
• /
• 2003

o In order to start SIP Project .Marketing (& ASIC team) should present biz planning, schedule, device/SIP specs., in SIP TFT prior to request SIP development for package development project. .In order to prevent (PCB) revision, test, burn-in, & quality strategy should be fixed by SIP TFT (PE/Test, QA) prior to request for PKG development. .Target product price/cost, package/ test cost should be delivered and reviewed. o Minimum Information for PCB Design, Package Size, and Cost .(Required) package form factor: size, height, type (BGA, QFP), Pin count/pitch .(Estimated) each die size including scribe lane .(Estimated) pad inform. : count, pitch, configuration(in-line/staggered), (open) size .(Estimated) each device (I/O & Core) power (especially for DRAM embedded SIP) .SIP Block diagram, and net-list using excel sheet format o Why is the initial evaluation important\ulcorner .The higher logic power resulted in spec. over of DRAM Tjmax. This caused business drop longrightarrow Thermal simulation of some SIP product is essential in the beginning stage of SIP business planning (or design) stage. (i.e., DRAM embedded SIP) .When SIP is developed using discrete packages, the I/O driver Capa. of each device may be so high for SIP. Since I/O driver capa. was optimized to discrete package and set board environment, this resulted in severe noise problem in SIP. longrightarrow In this case, the electrical performance of product (including PKG) should have been considered (simulated) in the beginning stage of business planning (or design).

• Proceedings of the KIEE Conference
• /
• 2007.07a
• /
• pp.262-263
• /
• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• The Optical Journal
• /
• s.117
• /
• pp.23-25
• /
• 2008

RF embedded 기판의 기술은 Module과 Package라는 응용 제품을 거치면서 최종적으로는 기존의 여러 가지 제품의 Mother Board(특히 휴대폰)에 접목 시키기 위한 노력이 계속 진행되고 있다. 업계 및 Research 기관의 조사 결과에 따르면 PCB 시장의 성장세와 맞물려 Embedded 시장규모는 큰 폭의 상승이 예상된다. 본 고에서는 높은 유전율을 가지는 강유전체 물질의 Embedded capacitor 적용을 위해 레이저 기술을 전자부품 제조현장에 적용하는 연구의 진행상황을 소개하고자 한다.