• Journal of Digital Contents Society
• /
• v.10 no.4
• /
• pp.493-499
• /
• 2009

Three methods frequently used for Hangul display in computer systems are Standard Johab Code in which each of Hangul consonants and vowels is given a 5-bit code and each syllable created by combining them forms a 2-byte code, Standard Wansung Code in which each of all the syllables generally used for Hangul presentation forms a 2-byte code, and Unicode in which each syllable in most of the world's language systems is given a unique code so that it allows computers to consistently represent and manipulate them in a unified manner. An embedded system in general has a lower processing power and a limited amount of storage space, compared to a personal compute(PC) system. According to its usage, however, the former may have a processing power equal to that of the latter. Hence, when Hangul display needs to be adopted, an embedded system must choose a display method suitable for its own resource environment. This paper introduces a TFT LCD initialization method and pixel display functions of an LN2440SBC embedded board on which an LP35, a 3.5" TFT LCD kit, is attached. Using the initialization and pixel display functions, in addition, we compare three aforementioned Hangul display methods, in terms of their processing speeds and amounts of memory space required. According to experiments, Standard Johab Code requires less amount of memory space but more processing time than Standard Wansung Code, and Unicode requires the largest amount of memory space but the least processing time.

• The KIPS Transactions:PartA
• /
• v.14A no.3 s.107
• /
• pp.173-184
• /
• 2007

Garbage collection in the Java virtual machine is a core function that relieves application programmers of difficulties related to memory management. In this paper, we evaluate and analyze the performance of GenGC and GenRGC, garbage collectors for embedded Java virtual machines. For performance evaluation, we employ CVM, a real embedded Java virtual machine developed by Sun Microsystems, Inc., as a platform and also use a widely-used SpecJVM98 as a set of benchmark programs. To compare the performance of GenGC and GenRGC, we first evaluate the time of garbage collection and the delay time caused by garbage collection. Second, for more detailed performance analysis of GenRGC, we evaluate the time of garbage collection and the delay time caused by garbage collection while changing the sizes of a block and a frame. Third, we analyze the size of storage space required for performing GenRGC, and show GenRGC to be suitable for embedded environment with a limited mont of memory. Since CVM is the most representative one of embedded Java virtual machines, this performance study is quite meaningful in that we can predict the performance of garbage collectors in real application environments more accurately.

• International journal of advanced smart convergence
• /
• v.6 no.1
• /
• pp.26-31
• /
• 2017

When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2000.07a
• /
• pp.751-754
• /
• 2000

When charge-trap SONOS cells are used flash memory, the tunneling program/erase condition to minimize the generation of interface traps was investigated. SONOSFET NVSM cells were fabricated using 0.35$\mu\textrm{m}$ standard memory cell embedded logic process including the ONO cell process. based on retrograde twin-well, single-poly, single metal CMOS process. The thickness of ONO triple-dielectric for memory cell is tunnel oxide of 24${\AA}$, nitride of 74 ${\AA}$, blocking oxide of 25 ${\AA}$, respectively. The program mode(Vg: 7,8,9 V, Vs/Vd: -3 V, Vb: floating) and the erase mode(Vg: -4,-5,-6 V, Vs/Vd: floating, Vb: 3V) by modified Fowler-Nordheim(MFN) tunneling were used. The proposed programming condition for the flash memory of SONOSFET NVSM cells showed less degradation($\Delta$Vth, S, Gm) characteristics than channel MFN tunneling operation. Also the program inhibit conditions of unselected cell for separated source lines NOR-tyupe flash memory application were investigated. we demonstrated that the program disturb phenomenon did not occur at source/drain voltage of 1 V∼4 V and gate voltage of 0 V∼4.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.32 no.3
• /
• pp.487-499
• /
• 2022

Machine learning such as deep learning have been widely used in recent years. Recently deep learning is performed in a trusted execution environment such as ARM TrustZone to improve security in edge devices and embedded devices with low computing resource. To mitigate this problem, we propose TPMP that efficiently uses the limited memory of TEE through DNN model partitioning. TPMP achieves high confidentiality of DNN by performing DNN models that could not be run with existing memory scheduling methods in TEE through optimized memory scheduling. TPMP required a similar amount of computational resources to previous methodologies.

• Proceedings of the KIEE Conference
• /
• 2003.11b
• /
• pp.211-214
• /
• 2003

Current VOD embodiment way is embodied using PC base. However, achieved research that embody this by Embedded System that PC base is not. OS of this system used WindowsCE.net and x86core used having built-ined SC1200(National company's Geode's familys) by CPU and memory used 128MByte SDRAM. Used Mpeg Decoder for processing of video data, and used Enthernet Controller for Internet. Composite, component, S-Video of video output section of this system is and select one of these and connect on TV and did so that get into action. Actuality implementation manufactured necessary BIOS, WinodwsCE.NET Porting, DeviceDriver in system development and necessary simple Application in action confirmation, and Video Player used Window Media Player had included to WindowsCE.net. Therefore, treatise that see to supplement shortcomings of VOD service been embodying in current PC in Embedded System's form embody that there is sense do can.

• The Journal of the Acoustical Society of Korea
• /
• v.30 no.8
• /
• pp.461-467
• /
• 2011

Accurate classification of input signals is the key prerequisite for variable bit-rate coding, which has been introduced in order to effectively utilize limited communication bandwidth. Especially, recent surge of multimedia services elevate the importance of speech/music classification. Among many speech/music classifier, the ones based on support vector machine (SVM) have a strong selling point, high classification accuracy, but their computational complexity and memory requirement hinder their way into actual implementations. Therefore, techniques that reduce the computational complexity and the memory requirement is inevitable, particularly for embedded systems. We first analyze implementation of an SVM-based classifier on embedded systems in terms of execution time and energy consumption, and then propose two techniques that alleviate the implementation requirements: One is a technique that removes support vectors that have insignificant contribution to the final classification, and the other is to skip processing some of input signals by virtue of strong correlations in speech/music frames. These are post-processing techniques that can work with any other optimization techniques applied during the training phase of SVM. With experiments, we validate the proposed algorithms from the perspectives of classification accuracy, execution time, and energy consumption.

• The KIPS Transactions:PartA
• /
• v.14A no.1 s.105
• /
• pp.55-62
• /
• 2007

Uptime of embedded processors for mobile devices are dependent on battery consumption. Especially the large portion of power consumption is known to be due to cache management in embedded processors. This paper proposes an energy efficient data cache structure for high performance embedded processors. High performance prefetching data cache issues prefetching instructions before issuing demand-fetch instructions based on reference predictions. These prefetching instruction bring reduction on memory delay by improving cache hit ratio, but on the other hand those increase energy consumption in proportion to the number of prefetching instructions. In this paper, we adopt tag history table on prefetching data cache for reducing energy consumption by minimizing parallel tag comparison. Experimental results show the proposed data cache improves performance on energy consumption as well as memory delay.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.108-109
• /
• 2012

This talk will begin with the demonstration of facile synthesis of silicon nanostructures using the magnesiothermic reduction on silica nanostructures prepared via self-assembly, which will be followed by the characterization results of their performance for energy storage. This talk will also report the fabrication and characterization of highly porous, stretchable, and conductive polymer nanocomposites embedded with carbon nanotubes (CNTs) for application in flexible lithium-ion batteries. It will be presented that the porous CNT-embedded PDMS nanocomposites are capable of good electrochemical performance with mechanical flexibility, suggesting these nanocomposites could be outstanding anode candidates for use in flexible lithium-ion batteries. Directed self-assembly (DSA) of block copolymers (BCPs) can generate uniform and periodic patterns within guiding templates, and has been one of the promising nanofabrication methodologies for resolving the resolution limit of optical lithography. BCP self-assembly processing is scalable and of low cost, and is well-suited for integration with existing semiconductor manufacturing techniques. This talk will introduce recent research results (of my research group) on the self-assembly of Si-containing block copolymers for the achievement of sub-10 nm resolution, fast pattern generation, transfer-printing capability onto nonplanar substrates, and device applications for nonvolatile memories. An extraordinarily facile nanofabrication approach that enables sub-10 nm resolutions through the synergic combination of nanotransfer printing (nTP) and DSA of block copolymers is also introduced. This simple printing method can be applied on oxides, metals, polymers, and non-planar substrates without pretreatments. This talk will also report the direct formation of ordered memristor nanostructures on metal and graphene electrodes by the self-assembly of Si-containing BCPs. This approach offers a practical pathway to fabricate high-density resistive memory devices without using high-cost lithography and pattern-transfer processes. Finally, this talk will present a novel approach that can relieve the power consumption issue of phase-change memories by incorporating a thin $SiO_x$ layer formed by BCP self-assembly, which locally blocks the contact between a heater electrode and a phase-change material and reduces the phase-change volume. The writing current decreases by 5 times (corresponding to a power reduction of 1/20) as the occupying area fraction of $SiO_x$ nanostructures varies.

• The KIPS Transactions:PartA
• /
• v.12A no.7 s.97
• /
• pp.571-582
• /
• 2005

NAND flash memory has advantages of non-volatility, little power consumption and fast access time. However, it suffers from inability that dose not provide to update-in-place and the erase cycle is limited. Moreover, the unit of read and write operations is a page. A NAND flash file system called YAFFS has been proposed. But YAFFS has several problems to be addressed. In this paper, the Reliable Flash File System(RFFS) for NAND flash memory is designed and evaluated. In designing a file system the following four issues must be considered in particular for the design: (i) to minimize a repairing time when the system fault occurs, (ii) to balance the number of block erase operations by offering wear leveling policy, and (iii) to reduce turnaround time of memory operations by reducing the amount of data written. We demonstrate and evaluate the performance of the proposed schemes.