• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.674-676
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• 2008

An electrostatic discharge (ESD) or a noise supplied from the outside has an effect on communication between the timing controller (TCON) and the memory element (EEPROM) through the interface between the timing controller and the memory element in liquid crystal displays (LCD). Therefore, we must apply ESD protection methods to LCD operating circuits for a normal operation. Our ESD protection circuit is to prevent from bi-directional communication errors between TCON and EEPROM due to an electrostatic discharge (ESD).

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.908-910
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• 2007

Thin Film Transistor (TFT) manufacturing process is complicated. Electrostatic discharge (ESD) occurs during every process step. This paper describes ESD phenomena in terms of TFT design and processing flow. The abnormal contact between equipment and glass is found out to be the key reason causing ESD.

• 한국안전학회지
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• 제17권4호
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1289-1294
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• 2008

Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.24-25
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• 2008

An Electrostatic discharge (ESD) protection has been a very important reliability issue in microelectronics, especially for RF (Radio Frequency) integrated circuits (ICs). This paper reviews design and analysis of on-chip ESD (electrostatic discharge) protection circuits for RF applications. Key issues in RF ESD protection, design methods, and RF ESD protection solutions are discussed.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.2017-2032
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• 2018

This study presents, for the first time, state-of-the art review of the various techniques for the modeling of the electrostatic discharge (ESD) generators for the ESD analysis and testing. After a brief overview of the ESD generator, the study provides an in-depth review of ESD generator modeling (analytical, circuit and numerical modeling) techniques for the contact discharge mode. The proposed techniques for each modeling approach are compared to illustrates their differences and limitations.

• 한국자기학회지
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• 제12권5호
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• pp.168-173
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• 2002

본 연구에서는 인체모델(humman body model; HBM)을 터널링 자기저항(tunneling magneto resistance; TMR)소자에 연결하여 정전기에 대한 방전특성을 연구하였다. 이를 위해 제조된 TMR 시편을 전기적 등가회로 바꿔 HBM에 연결하여 PSPICE를 이용해 시뮬레이션 하였다. 이러한 등가회로에서 접합부분의 모델링 요소들의 값을 변화시켜 방전특성을 관찰할 수 있었다. 그 결과 시편의 저항과 정전용량 성분의 값이 다른 요소들에 비해 수배에서 수백 배까지 커서 정전기 방전(electrostatic discharge; ESD) 민감도를 좌우하는 주요한 요소임을 알 수 있었다. 여기에서 ESD현상에 대한 내구성을 향상시키기 위해서는 정전용량을 증가시키는 것 보다 접합면과 도선의 저항값을 줄이는 것이 유리하다. 그리고 직류 전압에 대해 절연층의 전위 장벽이 낮아져 많은 전류가 흐르게 되는 항복(breakdown)전압과 셀의 물리적 구조 및 성질이 변형되어 회복되지 못하는 파괴(failure)전압을 측정하여 DC 상태에서의 내구성을 연구하였다. 이 결과를 HBM 전압에 대한 파괴 전압으로 간주하여 TMR 소자가 견딜 수 있는 HBM 전압을 예측할 수 있었다.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.2033-2044
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• 2018

This study presents states-of-the art overview of the system level electrostatic discharge (ESD) analysis and testing. After brief description of ESD compliance standards and ESD coupling mechanisms, the study provides an in-depth review and comparison of the various techniques for the system level ESD coupling analysis using time and frequency domain techniques, full wave electromagnetic modeling and hybrid modeling. The methods used for improving system level ESD testing using troubleshooting and determining the root causes of soft failures, the optimization of ESD testing and the countermeasures to mitigate ESD problems are also discussed.

• 전자공학회논문지
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• 제51권8호
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• pp.195-201
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• 2014

본 논문에서는 도광판(LGP, Light Guide Panel)의 미세먼지 세정을 위해 건식 점착롤 제진과 코로나 대전을 이용한 제전(ESD, electrostatic discharge) 방식을 적용한 건식 세정 장치를 개발한다. 이를 위해 점착롤 제진과 제전 방식을 혼합 적용할 수 있는 세정 메커니즘을 설계하고, LGP를 자동으로 로딩/언로딩 및 이송할 수 있는 장치를 설계하고 구현한다. 그리고 이물질 및 미세먼지 세정 실험을 통해 개발된 시스템이 안정적으로 동작함을 확인하였다.