• Journal of the Microelectronics and Packaging Society
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• v.22 no.3
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• pp.9-17
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• 2015

After its inception in 1994, the Journal of the Microelectronics and Packaging Society has continued to make significant strides in the number and quality of publications within its field. The interest in the microelectronics and packaging research has become more critical as consumer electronic products continue its increasing trend towards thinner and lighter devices that tests the boundaries of electronic devices. This study utilizes social network analysis of all published literature in the Journal for the past 22 years. Using the keywords and abstracts available within each individual article, the publications within the Journal has focused on major topics covering (1) flip chip, (2) reliability, (3) Cu, (4) IMC (intermetallic compounds), and (5) thin film. Using the social network relationship between keywords within articles, flip chip was closely associated with reliability, BGA (ball grid array), contact resistance, electromigration in many of the published research works within the Journal. From the centrality analysis, it was found that flip chip, reliability, Cu, thin film, IMC, and RF (radio frequency) to have a high degree of centrality suggesting these key areas of research have relatively high connectivity with other research topics within the Journal and is central to many of the research fields within the micro-electronics and packaging area. The cohesiveness analysis showed research clustering of five major cohesive sub-groups and was mapped to better understand the major area of research within this field. Research within the field of micro-electronics and packaging converges many disciplines of science and engineering. The continued evolution within this field requires an understanding of the rapidly changing industry environment and the consumer needs.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.29-33
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• 2000

MEMS, Micro Electro-Mechanical Systems, present one of the greatest advanced packaging challenges of the next decade. Historically hybrid technology, generally thick film, provided sensors and actuators while integrated circuit technologies provided the microelectronics for interpretation and control of the sensor input and actuator output. Brought together in MEMS these technical fields create new opportunities for miniaturization and performance. Integrated circuit processing technologies combined with hybrid design systems yield innovative sensors and actuators for a variety of applications from single crystal silicon wafers. MEMS packages, far more simple in principle than today's electronic packages, provide only physical protection to the devices they house. However, they cannot interfere with the function of the devices and often must actually facilitate the performance of the device. For example, a pressure transducer may need to be open to atmospheric pressure on one side of the detector yet protected from contamination and blockage. Similarly, an optical device requires protection from contamination without optical attenuation or distortion being introduced. Despite impediments such as package standardization and complexity, MEMS markets expect to double by 2003 to more than ＄9 billion, largely driven by micro-fluidic applications in the medical arena. Like the semiconductor industry before it. MEMS present many diverse demands on the advanced packaging engineering community. With focused effort, particularly on standards and packaging process efficiency. MEMS may offer the greatest opportunity for technical advancement as well as profitability in advanced packaging in the first decade of the 21st century! This paper explores MEMS packaging opportunities and reviews specific technical challenges to be met.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.7-12
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• 2012

Sn whiskers are a serious cause of failure in electronic devices as they create short circuits. Sn whisker growth and mitigation have been investigated by many Japanese consortia including JEITA and JAXA. This paper gives an overview about recent researches of JEITA and JAXA.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.1-9
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• 2013

Recently flexible electronic devices have attracted a great deal of attention because of new application possibilities including flexible display, flexible memory, flexible solar cell and flexible sensor. In particular, development of flexible memory is essential to complete the flexible integrated systems such as flexible smart phone and wearable computer. Research of flexible memory has primarily focused on organic-based materials. However, organic flexible memory has still several disadvantages, including lower electrical performance and long-term reliability. Therefore, emerging research in flexible electronics seeks to develop flexible and stretchable technologies that offer the high performance of conventional wafer-based devices as well as superior flexibility. Development of flexible memory with inorganic silicon materials is based on the design principle that any material, in sufficiently thin form, is flexible and bendable since the bending strain is directly proportional to thickness. This article reviews progress in recent technologies for flexible memory and flexible electronics with inorganic silicon materials, including transfer printing technology, wavy or serpentine interconnection structure for reducing strain, and wafer thinning technology.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.1-10
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• 2009

Carbon nanotube(CNT)s have been considered as one of the most unique materials due to the their superior mechanical, thermal and electrical properties. Therefore, numerous studies have been performed for the utilization of CNTs. This review article focuses on the recent research trends on the utilization of CNTs for new interconnect materials in electronics packaging. Major contents mentioned are the direct interconnection technology using CNTs and the main properties of polymer/CNTs composite materials. This article is aimed at the reviewing of important results from the recent studies and providing the straightforward understanding of the results through the mutual analysis and a industrial viewpoint.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.35-40
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• 2018

Simple and useful synthetic process to control the morphology of block copolymers (BCPs) is required for implementation in various device applications. However, the conventional method to use colloidal templates is not enough to realize the production of pure and massive core-shell nanoparticles due to the cost-intensive complex process. Here, we introduce a novel and facile synthesis method to realize the formation of core-shell $SiO_x$ nanoparticle power by employing an immersion annealing of a sphere-forming poly(styrene-b-dimethylsiloxane) (PS-b-PDMS) BCP. We successfully obtained a PS-encapsulated $SiO_x$ nanoparticle with a diameter of ~20 nm. In addition, we analyzed how the mixing ratio of heptane/ethanol affects the BCP morphology of self-assembled PS-b-PDMS nanoparticles, showing a worm-like structure under the optimum immersion conditions. This useful approach is expected to be extendable to other solvent-based BCP synthesis, providing a new guideline for unique BCP production.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.8
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• pp.958-966
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• 2012

This paper presents a compact bluetooth/WiFi dual-mode dual-band RF front-end module(FEM) is realized by low temperature co-fired ceramic(LTCC) technology. The proposed RF front-end module consists of a diplexer, baluns in the LTCC substrate, and an SPDT switch, an SP3T switch on the LTCC substrate. In order to reduce the module size and increase integration level, the proposed diplexer and balun are designed using LC lumped elements. The parasitic elements caused by coupling effect between metal pattern layers and ground plane layer are considered during the design. The fabricated dual-mode RF front-end module has 13 pattern layers including three inner ground layers and it occupies less than $3.0mm{\times}3.7mm{\times}0.66mm$.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.269-272
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• 2004

Printed circuit boards (PCB) replaced conventional wiring in most electronic equipment I, reducing the size and weight of electronic equipment while improving reliability, uniformity, precision and performance. PCB is used in all kinds of electronic products because they can be mass-produced with very high circuit density and also enable easier trouble-shooting. This paper presents the analyses of the patent information of Build-up PCB which is seen as the most promising solution, as its substrate supports multi-level packaging, thinner board profiles and smaller pitches.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.42-45
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• 2018

As The semiconductor decrease from 10 nanometer to 7 nanometer, It is suggested that "More than Moore" is needed to follow Moore's Law, which has been a guide for the semiconductor industry. Fan-Out Wafer Level Package(FOWLP) is considered as the key to "More than Moore" to lead the next generation in semiconductors, and the reasons are as follows. the fan-out WLP does not require a substrate, unlike conventional wire bonding and flip-chip bonding packages. As a result, the thickness of the package reduces, and the interconnection becomes shorter. It is easy to increase the number of I / Os and apply it to the multi-layered 3D package. However, FOWLP has many issues that need to be resolved in order for mass production to become feasible. One of the most critical problem is the warpage problem in a process. Due to the nature of the FOWLP structure, the RDL is wired to multiple layers. The warpage problem arises when a new RDL layer is created. It occurs because the solder ball reflow process is exposed to high temperatures for long periods of time, which may cause cracks inside the package. For this reason, we have studied warpage in the FOWLP structure using commercial simulation software through the implementation of the reflow process. Simulation was performed to reproduce the experiment of products of molding compound company. Young's modulus and poisson's ratio were found to be influenced by the order of influence of the factors affecting the distortion. We confirmed that the lower young's modulus and poisson's ratio, the lower warpage.