• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.19-26
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• 2010

We found that saturated water vapor pressure is the most dominant stress factor for the degradation phenomenon in the package for high-power phosphor-converted white light emitting diode (high power LED). Also, we proved that saturated water vapor pressure is effective acceleration stress of LED package degradation from an acceleration life test. Test conditions were $121^{\circ}C$, 100% R.H., and max. 168 h storage with and without 350 mA. The accelerating tests in both conditions cause optical power loss, reduction of spectrum intensity, device leakage current, and thermal resistance in the package. Also, dark brown color and pore induced by hygro-mechanical stress partially contribute to the degradation of LED package. From these results, we have known that the saturated water vapor pressure stress is adequate as the acceleration stress for shortening life test time of LED packages.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.3
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• pp.167-173
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• 2011

Since many blood pressure pulse analyzer made to measurement of a pulse wave in quantitative way has been started, some sorts of pressure sensors are being developed. The result could differ and this cause either type of sensor or module shape, when pulse wave is measured. In this paper, calculate and compare the pressure sensor's stress distribution according to thickness of PDMS coating and existence of guide through Finite Element Method. As a result, the center of pressure sensor's stress increase as much as 24% as it is reduced as much as 0.3 mm that the PDMS coating thichness of pulse diagnostic sensor module, on the other hand the surrouding censor of center sensor's stress is reduced as much as 4.9%, and transmissive proportion of stress is small as little as 2.7%, When coating has guide.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.45 no.12
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• pp.1048-1058
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• 2017

One of the failure mechanism of spaceborne electronics is a fatigue fracture on solder joint under launch random vibration. Thus, a necessity of early diagnosis through the fatigue life evaluation on solder joint arises to prevent such potential risk of failure. The conventional life prediction methods cannot assure the accuracy of life estimation results if the packaging type changes, and also requires much time and effort to construct the analysis model of highly integrated PCB with various packaging types. In this study, we performed life prediction of PCB based on a reliability and life prediction tool of sherlock as a new approach for evaluating the structural reliability on solder joint, and those prediction results were validated by fatigue tests. In addition, we also investigated an influence of solder height on the fatigue life of solder joint. These results indicated that the Sherlock is applicable tool for evaluating the structural reliability of spaceborne electronic.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.1
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• pp.43-49
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• 2015

By the trends of electronic package to be smaller, thinner and more integrative, organic printed circuit board is required to be finer Cu trace pitch. This paper reports on a study of failure mechanism for PCB with fine Cu trace pitch using biased HAST. In weibull analysis of the biased HAST lifetime, it is found that the acceleration factor (AF) of between $135^{\circ}C/90%RH/3.3V$ and $130^{\circ}C/85%RH/3.3V$ is 2.079. A focused ion beam (FIB) was used to polish the cross sections to reveal details of the microstructure of the failure mode. It is found that $Cu_xO/Cu(OH)_2$ colloids and Cu dendrites were formed at anode (+) and at cathode (-), respectively. Thus, this gives the evidence that Cu dendrites formed at cathode by $Cu^{2+}$ ion migration lead to a short failure between a pair of Cu nets.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.15-24
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• 2014

Recently, a variety of printing technologies, including ink jet, gravure, and roll-to-roll (R2R) printing, has generated intensive interest in the application of flexible and wearable electronic devices. However, the actual use of printing technique is much limited because the sintering process of the printed nanoparticle inks remains as a huge practical drawback. In the fabrication of the conductive metal film, a post-sintering process is required to achieve high conductivity of the printed film. The conventional thermal sintering takes considerable sintering times, and requires high temperatures. For application to flexible devices, the sintering temperature should be as low as possible to minimize the damage of polymer substrate. Several alternative sintering methods were suggested, such as laser, halogen lamp, infrared, plasma, ohmic, microwave, and etc. Eventually, the new sintering technique should be applicable to large area, R2R, and polymer substrate as well as low cost. This article reviews progress in recent technologies for several sintering methods. The advantages and disadvantages of each technology will be reviewed. Several issues for the application in R2R process are discussed.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.31-35
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• 2006

This paper is studied on a protective control system for electrical fire used electrical characteristics of SCR and multilayer-type PTC thermistor. The PTC thermistor has characteristic or positive resistivity temperature coefficient according to the temperature variation, which is construction of a regular square and cube demarcation with $BaTiO_{3_}$Ceramics of positive temperature coefficient. Also PTC shows the phenomenon which is rapidly increased in the resistivity if the temperature is increased over Curie temperature point. This paper is proposed on a protective control system used multilayer-type PTC which is protected from electrical fire due to electric short circuit faults or overload faults. Some experimental results of the proposed apparatus is confirmed to the validity of the analytical results.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.57-61
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• 2006

Fuel cells are direct current (DC) power generators. They generate electricity through an electrochemical process that converts the energy stored in a fuel directly into electricity. Fuel cells have many benefits, which produce no particulate matter, nitrogen or sulfur oxides. And they have few moving parts and produce little or no noise. When fueled by hydrogen, they yield only heat and water as byproducts. Their wide application can reduce our dependence on fossil fuels and foreign sources of petroleum. This paper is studied on a high efficiency power conditioning system (PCS) applied to the proton exchange membrane fuel cell (PEMFC) generation system. This paper is designed to a novel PCS circuit topology of high efficiency. Some experimental results of the proposed PCS is confirmed to the validity of the analytical results.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.63-72
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• 2006

Mobile products, such as cellular phones, PDA and notebook, are subjected to many different mechanical loads, which include bending, twisting, impact shock and vibration. In this study, a cyclic bending test of the BGA package was performed to evaluate the fatigue life. Special bending tester, which was suitable for electronic package, was developed using an electromagnetic actuator. A nonlinear finite element model was used to simulate the mechanical bending deformation of solder joint in BGA packages. The fatigue life of lead-free (95.5Sn4.0Ag0.5Cu) solder joints was compared with that of lead-contained (63Sn37Pb). When the applied load to the specimen is small, the lead-free solder has longer fatigue life than lead-contained solder. The fatigue crack is initialized at the exterior solder joints and is propagated into the inner solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.37-41
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• 2014

One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about $0.3{\sim}0.5{\mu}m$ and the bump height after Cu electroplating only was about $1.1{\sim}1.4{\mu}m$. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.