• Journal of IKEEE
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• v.22 no.4
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• pp.886-895
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• 2018

This paper describes a hardware design of the Secure Hash Algorithm-3 (SHA-3) hash functions that are the latest version of the SHA family of standards released by NIST, and an implementation of ARM Cortex-M0 interface for security SoC applications. To achieve an optimized design, the tradeoff between hardware complexity and performance was analyzed for five hardware architectures, and the datapath of round block was determined to be 1600-bit on the basis of the analysis results. In addition, the padder with a 64-bit interface to round block was implemented in hardware. A SoC prototype that integrates the SHA-3 hash processor, Cortex-M0 and AHB interface was implemented in Cyclone-V FPGA device, and the hardware/software co-verification was carried out. The SHA-3 hash processor uses 1,672 slices of Virtex-5 FPGA and has an estimated maximum clock frequency of 289 Mhz, achieving a throughput of 5.04 Gbps.

• Journal of Broadcast Engineering
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• v.24 no.1
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• pp.32-40
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• 2019

Indoor location estimation studies are needed in various fields. The method of estimating the indoor position can be divided into a method using hardware and a method using no hardware. The use of hardware is more accurate, but has the disadvantage of hardware installation costs. Conversely, the non-hardware method is not costly, but it is less accurate. To estimate the location for AR game, you need to get the solution of the Perspective-N-Point (PnP). To obtain the PnP problem, we need three-dimensional coordinates of the space in which we want to estimate the position and images taken in that space. The position can be estimated through six pairs of two-dimensional coordinates matching the three-dimensional coordinates. To further increase the accuracy of the solution, we proposed the use of an additional non-coplanarity degree to determine which points would increase accuracy. As the non-coplanarity degree increases, the accuracy of the position estimation becomes higher. The advantage of the proposed method is that it can be applied to all existing location estimation methods and that it has higher accuracy than hardware estimation.

• Proceedings of the KOSOMBE Conference
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• v.1993 no.05
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• pp.113-115
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• 1993

In this paper, we proposed a speech support system of personal computer for the blind. The system is consist of hardware part and software part. The hardware part are consist of personal computer and sound card. The software part are consist of sound driver system, character table and sound output algorithm. This system can recognize inputted characters from keyboard and program produced character strings.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.629-630
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• 2006

This paper presented a hardware implementation of ARIA, which is Korean standard block ciphering algorithm. In this work, we proposed a improved architecture based on pipeline structure and confirmed that the design operates in a clock frequency of 101.7MHz and in throughput of 957Mbps in Xilinx FPGA XCV-1600E.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.187-190
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• 2004

This paper proposes an efficient hardware implementation of SPIHT(Set Partitoning In Hierarchical Tree) algorithm for image compression with the discrete wavelet transform. An efficient technique to scan the coefficients which are located in partitioned spatial orientation trees by DWT is considered in terms of counter fields for sorting pass and refinement pass. The proposed image compression method using SPIHT has been modeled in VHDL and has been implemented by use of both TMS320C6000 as a DSP and Virtex2 as a Xilinx FPGA.

• Journal of information and communication convergence engineering
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• v.11 no.2
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• pp.112-117
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• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• Journal of Multimedia Information System
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• v.5 no.4
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• pp.273-276
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• 2018

In video compression standards, the entropy coding is essential to the high performance compression because redundancy of data symbols is removed. Binary arithmetic coding is one of high performance entropy coding methods. However, the dependency between consecutive binary symbols prevents improving the throughput. For the throughput enhancement, a new probability model is proposed for encoding multi-symbols at one time. In the proposed method, multi-symbol encoder is implemented with only adders and shifters, and the multiplication table for interval subdivision of binary arithmetic coding is removed. Compared to the compression ratio of CABAC of H.264/AVC, the performance degradation on average is only 1.4% which is negligible.

• Proceedings of the Korea Information Processing Society Conference
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• 2022.05a
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• pp.294-297
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• 2022

본 논문에서는 비평탄 지형 보행이 가능한 이동형 로봇의 설계 최종 목적에 최적화된 12자유도 소형 4족 로봇의 하드웨어를 설계하였으며, 비평탄 지형을 극복하기 위한 지능적인 보행을 설계하고 그에 따른 각 관절별 모터들의 용량을 분석하고 시뮬레이션을 통해 최적의 파라미터값들을 도출한다

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05a
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• pp.23-26
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• 2003

본 논문은 웨이블릿 변환 과정을 통해서 분해한 영상을 Shapiro가 제안한 효율적인 영상 압축 방법인 EZW(Embedded Zerotree Wavelet)알고리즘을 하드웨어로 설계하였다. 이를 위한 하드웨어 구조를 제시하고 VHDL로 모델링 하여 FPGA를 통해 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.