• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.4-4
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• 2009

Surface analysis on defective wire-bonding pads are performed in flash memory assembly. Week wire bonding may cause a significant effect on the final product reliability, and the surface condition of the aluminum bond pads is critical in terms of product reliability. To find out possible week bonding on semiconductor interconnects, ball sheer test (BST) has been performed. On some defective or week bonded pads, we have investigated the surface contents, assuming that the week bonding is induced from the surface conditions. AES and XPS are employed for the quantitative surface analysis on defective dies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.447-450
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• 2001

Abstract-Si direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively. Components existed in the interlayer were analysed by using FT-lR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 2.4kgf/cm$^2$∼Max : 14.9kgf/cm$^2$).

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.859-864
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• 2003

We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.672-675
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• 1999

Si-to-Si electrostatic bonding was carried out by employing LSG interlayer instead of conventional Corning #7740 interlayer in order to improve bonding properties. The surface roughness and dielectric breakdown field of the LSG interlayers deposited on Si substrates were investigated. Also, the bonding interface, bonding strength and bonding mechanism were discussed for the electrostatically-bonded Si-Si wafer pairs having LSG interlayers.

• Journal of Welding and Joining
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• v.31 no.6
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• pp.77-83
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• 2013

3D packaging technology using TSV (Through Silicon Via)has been studied in the recent years to achieve higher performance, lower power consumption and smaller package size because electrical line is shorter electrical resistivity than any other packaging technology. To stack TSV chips vertically, reliable and robust bonding technology is required because mechanical stress and thermal stress cause fracture during the bonding process. Cu pillar/solder ${\mu}$-bump bonding process is usually to interconnect TSV chips vertically although it has weak shape to mechanical stress and thermal stress. In this study, we suggest Insert-Bump (ISB) bonding process newly to stack TSV chips. Through experiments, we tried to find optimal bonding conditions such as bonding temperature and bonding pressure. After ISB bonding, we observed microstructure of bump joint by SEM and then evaluated properties of bump joint by die shear test.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.164-167
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.171-171
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• 2008

본 연구는 초음파 알루미늄 웨지 및 금 볼 본딩을 동시에 적용 가능한 본딩 Pad의 금속학적 안정성을 고려한 표층전극 형성 방법에 관한 것이다. 특히, 이동통신 및 전장용 모듈의 복합 및 융합화로 LTCC기판 패키징에 있어서 다양한 본딩 기술이 요구되고 있다. 전통적인 interconnection 기술인 Au ball 본딩 및 초음파 에너지를 이용한 Al wedge 본딩 기술이 동시에 사용되어야 하는 패키지 구조의 경우 본딩 패드의 표층전극 설계는 서로 상충되는 조건이 요구된다. 따라서, 본 연구에서는 LTCC기판의 표층전극의 Metal finish 방법으로 이용되는 ENEPIG(무전해 Ni/Pd/Au도금)공법으로 Au ball 본딩 및 초음파 Al wedge 본딩을 동시에 가능하게 하는 solution을 제시하여 패키징 자유도뿐만 아니라 Interconnection 신뢰성을 확보할 수 있었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.338-341
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• 1996

Anodic bonding is a key technology for micromechanical components. The main advantages of this method can be formed in a batch process, over large areas, and is permanent and irreversible. In this paper, the bonding was performed at temperatures ranging from 300 to 450 $^{\circ}C$, voltages 400 to 1000 V, and times 10 to 30 minutes. The sizes of the Si and the Pyrex #7740 glass were 6 mm $\times$6 mm, respectively. Bonding processes and voids were observed by the optical microscope, and the composition of the anodic bonding interface was analyzed by the SIMS. Optimum condition of the anodic bonding was at temperature above 40$0^{\circ}C$ without regard to voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.4
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• pp.653-659
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• 2008

This paper describes the design of high power transistor packages using high power chip transistor dies, chip capacitors and a new wire bonding technique. Input impedance variation and output power performances according to wire inductance and resistance for internal matching are also discussed. A multi crossing type(MCT) wire bonding technique is proposed to replace the conventional stepping stone type(SST) wire bonding technique, and eventually to improve the output power performances of high power transistor packages. Using the proposed MCT wire bonding technique, it is possible to design high power transistor packages with highly improved output power compared to SST even the package size is kept to be the same.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.4
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• pp.275-280
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• 1999

The glass-to-glass electrostatic bonding process in vacuum environment was developed and the tubeless-packaged FED was fabricated based on the bonding process. The fabricated tubeless-packaged FED showed stable field emission characteristics and potential applicability to the FED tubeless packaging and vacuum in-line sealing.