• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.189-195
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• 2004

A 10 Gb/s limiting amplifier IC with the emitter area of $1.5{\times}10{\mu}m^2$ for optical transmission system was designed and fabricated with a AIGaAs/GaAs HBTs technology. In this stud)', we evaluated fine pitch bump using WL-CSP (Wafer Level-Chip Scale Packaging) instead of conventional wire bonding for interconnection. For this we developed WL-CSP process and formed fine pitch solder bump with the $40{\mu}m$ diameter and $100{\mu}m$ pitch on bonding pad. To study the effect of WL-CSP, electrical performance was measured and analyzed in wafer and package module using WL-CSP. In a package module, clear and wide eye diagram openings were observed and the riselfall times were about 100ps, and the output" oltage swing was limited to $600mV_{p-p}$ with input voltage ranging from 50 to 500m V. The Small signal gains in wafer and package module were 15.56dB and 14.99dB respectively. It was found that the difference of small signal gain in wafer and package module was less then 0.57dB up to 10GHz and the characteristics of return loss was improved by 5dB in package module. This is due to the short interconnection length by WL-CSP. So, WL-CSP process can be used for millimeter wave GaAs MMIC with the fine pitch pad.

• 디지털융복합연구
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• 제14권10호
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• pp.261-269
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• 2016

본 논문에서는 CATV 동축케이블 망에서 초고속인터넷 서비스를 제공하기 위한 네트워크 융복합의 새로운 기술을 제안하고, 1Gbps급 전송속도를 갖는 케이블 집선장치와 모뎀을 제작하였다. 이 기술은 기존 DOCSIS 규격의 결합(Bonding) 기술에 비해 제작비용을 낮출 수 있을 뿐만 아니라 채널 대역폭 조절에 따라 데이터 속도도 가변이 용이한 구조로 설계되었다. 실험결과에 따르면, 128QAM 컨볼루션 코드 레이트를 1/2, 2/3, 3/4, 5/6, 7/8로 변화시켰을 때, 데이터는 에러율이 0 상태에서 최대 299Mbps까지의 전송속도를 나타냈으며, 256QAM에서는 $10^{-5}$이내의 에러율 상태에서 342Mbps의 전송속도를 나타내었다. 본 논문의 결과를 활용하여, 채널 대역폭 200MHz를 확보하고 채널 상태에 따라 변조율과 부호율을 조정하면, 1Gbps 이상 전송속도가 가능하고, 기존 DOCSIS방식 보다 성능과 가격 면에서 경쟁력을 가질 것으로 기대된다.

• 대한전자공학회논문지SD
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• 제48권7호
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• pp.76-81
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• 2011

본 논문에서는 비아 절단 구조를 제안하고 2층 구조의 DRAM 패키지 기판 설계에 적용하여 낮은 임피던스를 가지는 파워 분배망(Power Distribution Network)을 구현하였다. 제안한 신규 비아 구조는 비아의 일부가 절단된 형태이고 본딩 패드와 결합하여 넓은 배선 면적을 필요로 하지 않는 장점을 가진다. 또한 비아 절단 구조를 적용한 설계에서는 본딩 패드에서 VSSQ까지의 배선 경로를 효과적으로 단축시킴으로써 PDN 임피던스를 개선시킬 수 있다. DRAM 패키지 기판 상의 윈도우 영역 형성과 동시에 비아의 일부 영역이 제거되므로 비아 절단 구조 제작을 위한 추가적인 공정은 없다. 또한 비아 홀 내부를 솔더 레지스트로 채움으로써 버(Burr) 발생을 최소화하였으며, 이를 패키지 기판 단면 촬영을 통해 검증하였다. 비아 절단 구조의 적용 및 VDDQ/VSSQ 배치에 의한 PDN 임피던스 변화를 검증하기 위해서 3차원 전자장 시뮬레이션 및 네트워크 분석기 측정을 통해 기존 방식을 적용한 패키지 기판과 비교 검증을 진행하였다. 신규 DRAM 패키지 기판은 대부분의 주파수 범위에서 보다 우수한 PDN 임피던스를 가졌으며, 이는 제안한 비아 절단 구조와 파워/그라운드 설계 배치가 PDN 임피던스 감소에 효과적임을 증명한다.

• Applied Science and Convergence Technology
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• 제26권5호
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• pp.110-113
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• 2017

The two-dimensional layered $MoS_2$ has high mobility and excellent optical properties, and there has been much research on the methods for using this for next generation electronics. $MoS_2$ is similar to graphene in that there is comparatively weak bonding through Van der Waals covalent bonding in the substrate-$MoS_2$ and $MoS_2-MoS_2$ heteromaterial as well in the layer-by-layer structure. So, on the monatomic level, $MoS_2$ can easily be exfoliated physically or chemically. During the $MoS_2$ field-effect transistor fabrication process of photolithography, when using water, the water infiltrates into the substrate-$MoS_2$ gap, and leads to the problem of a rapid decline in the material's yield. To solve this problem, an epoxy-based, as opposed to a water-based photoresist, was used in the photolithography process. In this research, a hydrophobic $MoS_2$ field effect transistor (FET) was fabricated on a hydrophilic $SiO_2$ substrate via chemical vapor deposition CVD. To solve the problem of $MoS_2$ exfoliation that occurs in water-based photolithography, a PPMA sacrificial layer and SU-8 2002 were used, and a $MoS_2$ film FET was successfully created. To minimize Ohmic contact resistance, rapid thermal annealing was used, and then electronic properties were measured.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1061-1065
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• 1995

To improve dielectric and mechanical properties of insulating composite by plasma surface treatment, new plasma surface treatment process is designed with concentric and hemi-circle electrodes system, the plasma, which is generated between anode and cathode, is induced to the upper side of the electrode system and treats the surface of the insulators. The optimal surface treatment condition is that pressure : 0.5[torr], flux density 100[gauss], discharge current : 500[mA] and treatment time : 3 minutes. The composite filled with glass cloth surface-treated by plasma shows the improvement in electric and mechanical properties, comparing non- and coupling agent-treated samples.

• 제어로봇시스템학회논문지
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• 제7권5호
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• pp.399-406
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• 2001

This paper presents a dynamic modeling and a sliding mode controller for the high-speed/high-accuracy position control system. The selected target system is the wire bonder assembly which is used in the semiconductor assembly process. This system is a reciprocating one around the pivot point that consists of VCM(voice coil motor) as an actuator and transducer horn as a bonding tool. For the modeling elements, the sys-tem is divided into electrical circuit, magnetic circuit and mechanical system. Each system is modeled using the bond graph method and united into the full system. Two major aims are considered in the design of the controller. The first one is that the horn must track the given reference trajectory. The second one is that the controller must be realizable by using the DSP board. Computer simulation and experimental results show that the designed sliding mode controller provides better performance than the PID controller.

• 한국정밀공학회지
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• 제17권2호
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• pp.89-96
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• 2000

This paper describes the characteristic of die finishing to obtain smooth surface using electro-chemical grinding after cutting process. Electro-chemical grinding is possible under lower load and tool wear comparing with those in the mechanical grinding. Conventionally, if the metal bonding material of the grinding wheel is directly t contacted with workpiece, the current is circulated without electrolytic phenomena. Sometimes, electrical discharge is occurred between tool and workpiece. To cope with this problem, the metal-resin bonded pellet was used in this study. This pellet is composed of optimal volume of metal and resin powders and its characteristics are changable with the each volume of powders. Finally, high efficient die finishing is realized using metal resin bonded pellet in electro-chemical grinding.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.60_61
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• 2009

최근 국내에서 345kV GIL(Gas Insulated Transmission Lines) 시스템의 실 계통 도입이 검토되고 있다. 현재까지 GIL은 원자력 발전소에서 주변압기로부터 스위치 야드까지 1km 미만의 거리에 소규모로 설치되어 운영되고 있다. 하지만 향후 본격적으로 GIL 시스템이 도입된다면 발전소 구내뿐만 아니라 수 km 이상 되는 송전급 선로에도 적용될 것이 예상된다. 현재 GIL의 시스(외함)는 100~120m 정도마다 접지를 하는 직접접지 형태를 취하고 있으나 시스에 흐르는 순환전류가 부하전류의 97% 이상 된다. 따라서 이에 따른 손실이 많이 발생되고 있어 도체에 흘릴 수 있는 허용전류 값이 감소하게 된다. 본 논문에서는 GIL 시스템에 크로스본드 접지방식을 적용하였을 때 시스 순환전류 감소 효과에 대해서 검토하고, 아울러 뇌써지나 스위칭 써지에 의한 절연통의 열화 등에 대비하기 위하여 절연통보호장치의 설치 방안에 대해서 검토하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 Techno-Fair 및 추계학술대회 논문집 전기물성,응용부문
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• pp.129-130
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• 2008

In this paper, optimal DRIE process conditions for fused quartz are experimentally determined by Taguchi method to develop high-performance inertial sensors based on the fused quartz material, which is known to have high Q-factors. Using Si layer as an etch mask, which was formed by previously developed bonding process of the fused quartz and Si wafer, fused quartz DRIE process was performed. Different 9 flow rate conditions of $C_4F_8$, $O_2$, He gas have been tested and the optimum combination of these factors was estimated. By this work, the ability to fabricate high aspect ratio fused quartz structure was confirmed.