• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.269-274
• /
• 1999

As the semiconductor industry enters the next century, we are facing to the technological changes and challenges. Optical lithography has driven by the miniaturisation of semiconductor devices and has been accompanied by an increase in wafer productivity and performance through the reduction of the IC image geometries. In the last decade, DRAM(Dynamic Random Access Memories) have been quadrupoling in level of integration every two years. Korean chip makers have been produced the memory devices, mainly DRAM, which are the driving force of IC＇s(Integrated Circuits) development and are the technology indicator for advanced manufacturing. Therefore, Korean chip makers have an important position to predict and lead the patterning technology. In this paper, we will be discussed the limitations of the optical lithography, such as KrF and ArF. And, post optical lithography technology, such as E-beam lithography, EUV and E-beam Projection Lithography shall be introduced.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.4
• /
• pp.274-282
• /
• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.77-77
• /
• 2011

These days, a growing demand for memory device is filled up with the flash memory and the dynamic random access memory (DRAM). Although DRAM is a reasonable solution for current demand, the universal novel memory with high density, high speed and nonvolatility, needs to be developed. Among various new memories, the magnetic random access memory (MRAM) device is considered as one of good candidate memories because of excellent features including high density, high speed, low operating power and nonvolatility. The etching of MTJ stack which is composed of magnetic materials and insulator such as MgO is one of the vital process for MRAM. Recently, MgO has attracted great interest in the MTJ stack as tunneling barrier layer for its high tunneling magnetoresistance values. For the successful realization of high density MRAM, the etching process of MgO thin films should be investigated. Until now, there were some works devoted to the investigations on etch characteristics of MgO thin films. Initially, ion milling was applied to the etching of MgO thin films. However, ion milling has many disadvantages such as sidewall redeposition and etching damage. High density plasma etching containing the magnetically enhanced reactive ion etching and high density reactive ion etching have been employed for the improvement of etching process. In this work, inductively coupled plasma reactive ion etching (ICPRIE) system was adopted for the improvement of etching process using MgO thin films and etching gas mixes of $CH_4$/Ar and $CH_4$/$O_2$/Ar have been employed. The etch rates are measured by a surface profilometer and etch profiles are observed using field emission scanning emission microscopy (FESEM). The effects of gas concentration and etch parameters such as coil rf power, dc-bias voltage to substrate, and gas pressure on etch characteristics will be systematically explored.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.38 no.5
• /
• pp.63-63
• /
• 2001

디바이스의 크기가 0.25㎛이하로 축소됨에 따라 DRAM(Dynamic Random Access Memory) 제조업체들은 칩 크기를 줄이고 지역적인 배선으로 사용하기 위해서 기존의 텅스텐-폴리사이드 비트-선에서 텅스텐 비트-선으로 대체하고 있다. 본 논문에서는 다양한 RTP 온도와 추가 이온주입을 사용하여 낮은 저항을 갖는 텅스텐 비트-선 제조 공정에 대해 다루었다. 그 결과 텅스텐 비트선 저항에 중요한 메계변수는 RTP Anneal 온도와 BF₂ 이온 주입 도펀트임을 알 수 있었다. 이러한 텅스텐 비트-선 공정은 고밀도 칩 구현에 중요한 기술이 된다.

• Journal of the Korean Ceramic Society
• /
• v.38 no.9
• /
• pp.782-786
• /
• 2001

Cobalt silicide has been employed to Embedded DRAM (Dynamic Random Access Memory) and Logic (EDL) as contact material to improve its speed. We have investigated the influences of Ti and TiN capping layers on cobalt-silicided Complementary Metal-Oxide-Semiconductor (CMOS) device characteristics. TiN capping layer is shown to be superior to Ti capping layer with respect to high thermal stability and the current driving capability of pMOSFETs. Secondary Ion Mass Spectrometry (SIMS) showed that the Ti capping layer could not prevent the out-diffusion of boron dopants. The resulting operating current of MOS devices with Ti capping layer was degraded by more than 10%, compared with those with TiN.

• Korean Journal of Optics and Photonics
• /
• v.15 no.1
• /
• pp.79-85
• /
• 2004

We report on a transmittance controlled photomask with phase patterns on the back quartz surface. Theoretical analysis for changes in illumination pupil shape with respect to the variation of size and density of backside phase patterns and experimental results for improvement of critical dimension uniformity on a wafer by using the transmittance controlled photomask are presented. As phase patterns for controlling transmittance of the photomask we used etched contact-hole type patterns with 180" rotative phase with respect to the unetched region. It is shown that pattern size on the backside of the photomask must be made as small as possible in order to keep the illumination pupil shape as close as possible to the original pupil shape and to achieve as large an illumination intensity drop as possible at a same pattern density. The distribution of illumination intensity drop suitable for correcting critical dimension error was realized by controlling pattern density of the contact-hole type phase patterns. We applied this transmittance controlled photomask to a critical layer of DRAM (Dynamic Random Access Memory) having a 140nm design rule and could achieve improvement of the critical dimension uniformity value from 24.0 nm to 10.7 nm in 3$\sigma$.TEX>.

• Korean Journal of Optics and Photonics
• /
• v.18 no.1
• /
• pp.74-78
• /
• 2007

We report theoretical and experimental results for application of transmittance-controlled photomask technology to ArF lithography. The transmittance-controlled photomask technology is thought to be a promising technique fo critical dimension (CD) uniformity correction on a wafer by use of phase patterns on the backside of a photomask. We could theoretically reproduce experimental results for illumination intensity drop with respect to the variation of backside phase patterns by considering light propagation from the backside to the front side of a photomask at the ArF lithography wavelength. We applied the transmittance-controlled photomask technology to ArF lithography for a critical layer of DRAM (Dynamic Random Access Memory) having a 110-nm design rule and found that the in-field CD uniformity value was improved from 13.8 nm to 9.7 nm in $3{\sigma}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.2
• /
• pp.116-125
• /
• 2006

We have presented a nanoelectromechanical (NEM) model based on atomistic simulations. Our models were applied to a NEM device as called a nanotube random access memory (NRAM) operated by an atomistic capacitive model including a tunneling current model. We have performed both static and dynamic analyses of a NRAM device. The turn-on voltage obtained from molecular dynamics simulations was less than the half of the turn-on voltage obtained from the static simulation. Since the suspended carbon nanotube (CNT) oscillated with the amplitude for the oscillation center under an externally applied force, the quantity of the CNT-gold interaction in the static analysis was different from that in the dynamic analysis. When the gate bias was applied, the oscillation centers obtained from the static analysis were different from those obtained from the dynamics analysis. Therefore, for the range of the potential difference that the CNT-gold interaction effects in the static analysis were negligible, the vibrations of the CNT in the dynamics analysis significantly affected the CNT-gold interaction energy and the turn-on voltage. The turn-on voltage and the tunneling resistance obtained from our tunneling current model were in good agreement with previous experimental and theoretical works.

• Journal of Advanced Navigation Technology
• /
• v.14 no.5
• /
• pp.767-774
• /
• 2010

Due to advantages of NAND flash memory such as non-volatility, low access latency, low energy consumption, light weight, small size and shock resistance, it has become a better alternative over traditional magnetic disk drives, and has been widely used. Traditional DBMSs including mobile DBMSs may run on flash memory without any modification by using Flash Translation Layer (FTL), which emulates a random access block device to hide the characteristics of flash memory such as "erase-before-update". However, most existing FTLs are optimized for file systems, not for DBMSs, and traditional DBMSs are not aware of them. Also, traditional DBMSs do not consider the characteristics of flash memory. In this paper, we propose a flash-conscious storage system for DBMSs that utilizes flash memory as a main storage medium, and carefully put the characteristics of flash memory into considerations. The proposed flash-conscious storage system exploits log records to avoid costly update operations. It is shown that the proposed storage system outperforms the state.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.95-96
• /
• 2009

A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.