• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.61 no.2
• /
• pp.324-328
• /
• 2012

A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.

• 제어로봇시스템학회:학술대회논문집
• /
• 1990.10b
• /
• pp.1327-1331
• /
• 1990

A new dual loop controller using color LCD bar graphs with LED back lights has been developed. An optional memory card is used to load or save the controller configuration, which may be a preprogrammed standard package or a user-programmed configuration, in addition to the built-in functions ready for user selection. The bar-graph display is selectable for single-loop or dual-loop use. A high grade of self-tuning functions using a modeling technique is built-in as standard. The controller can accommodate optional plug-in modules for thermocouples, communication, etc. All the options are fully field upgradable.

• Journal of the Korean Society for Precision Engineering
• /
• v.16 no.3 s.96
• /
• pp.154-163
• /
• 1999

In this paper, an ultra precision positioning system has been developed using dual servo loop control. For positioning system having long distance with ultra precision , the combination of global stage and micro stage was required. A servo motor based ball screw is used as a global stage and the piezo actuator as a micro stage. For the improvement of positional precision, the digital Chebyshev filter is implemented in the developed to dual servo system. Therefore, the positional repeatability has been achieved within ${\pm}$ 10 mm, and this technique can be applied to develop precision semiconductor equipments such as lithography steppers and probers.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.271-274
• /
• 1999

This paper proposes a simple architecture of digital dividing block in dual-modulus prescaler phase-locked loop used in the wireless communication. Proposed architecture eliminates a swallow counter in the conventional one and demonstrates the advantages in reducing the power consumption and the gate-counts. Therefore, it is suitable for small die area and low power applications. The circuit is designed in a standard 0.35${\mu}{\textrm}{m}$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.1
• /
• pp.74-84
• /
• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of the Semiconductor & Display Technology
• /
• v.6 no.1 s.18
• /
• pp.31-36
• /
• 2007

Effect of coulomb friction and backlash on the single loop position control has been studied for the precision position control. We have showed the limit cycle on the single loop system which used a ball screw that had the backlash. Also, we have made an inner loop with a classical velocity and torque controller which was forcing the current of d axis to be zero by using a permanent-magnet synchronous motor and composed the outer loop with linear encoder for sensing a position of the loader. Also, we have used least squares fit(LSF) observer for reducing noise when we got velocity from position outputs. We have shown a good result by using the dual loop through simulation and experiment.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.819-825
• /
• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.27 no.2C
• /
• pp.191-200
• /
• 2002

A frequency synthesizer that can be used in IMT-2000 was designed and fabricated using dual loop PLL(Phase Locked Loop) in this paper. For improving phase noise characteristic two loops, reference loop and main loop, were divided. Phase noise was improved by transformed clamp type voltage controled oscillator and optimizing loop bandwidth in reference loop. And voltage controlled oscillator open loop gain in main loop. Fabricated the frequency synthesizer had 1.81GHz center frequency, 160MHz tuning range, 13.5dBm output power and -119.73dBc/Hz low phase noise characteristic.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.87-90
• /
• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.738-740
• /
• 2004

The disturbance observer is effective in enhancing the performance of position control in high speed optical disk drive systems(ODDS). It is known that error based modified disturbance observer (EM-DOB) is more effective structure than general DOB. It has a simple structure and realization, but it loses robustness. We propose a dual modified disturbance observer(Dual mDOB). It consists of internal loop EM-DOB and external loop DOB. Those loops are designed for different objects. We see that the dual mDOB is an effective method for tracking performance.