• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.152-156
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• 2013

This paper presents a fast-lock dual-loop successive approximation register-controlled duty-cycle corrector (SARDCC) circuit using a mixed (binary+sequential) search algorithm. A wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy have been achieved by utilizing the dual-loop architecture and the binary search SAR that achieves the fast duty-cycle correcting property. By transforming the binary search SAR into a sequential search counter after the first DCC lock-in, the proposed dual-loop SARDCC keeps the closed-loop characteristic and tracks variations in process, voltage, and temperature (PVT). The measured duty cycle error is less than ${\pm}0.86%$ for a wide input duty-cycle range of 15-85 % over a wide frequency range of 0.5-2.0 GHz. The proposed dual-loop SARDCC is fabricated in a 0.18-${\mu}m$, 1.8-V CMOS process and occupies an active area of $0.075mm^2$.

• 한국정보통신학회논문지
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• 제15권7호
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• pp.1552-1558
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• 2011

본 논문에서는 전압제어지연단(Voltage Controlled Delay Line : VCDL)을 이용하여 기존의 위상고정루프와 다른 형태의 위상 지연고정루프(Phase Delay Locked Loop)를 제안하였다. 이 구조를 이용하여 기존의 위상고정루프의 2차 또는 3차 루프필터(Loop Filter)를 단하나의 커패시터로 구현하여 칩의 크기를 크게 줄였다. 새로이 제안하는 듀얼루프 위상 자연고정루프에서는 전압제어지연단 경로의 커패시터와 전하펌프의 전류 크기를 조절함으로서 작은 이득 값을 가지는 전압제어지연단을 사용할 수 있다. 제안된 회로는 $0.18{\mu}m$ CMOS 공정의 파라미터를 이용하여 Hspice로 시뮬레이션을 수행하고 회로의 동작을 검증하였다.

• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2000년도 추계학술대회논문집
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• pp.237-242
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• 2000

The areal recording density of HDD(Hard Disk Drive) has been increasing by about 60% a year. In order to achieve high areal density, less track pitch is expected and more servo bandwidth is required. Dual stage actuator and servo controller for HDD have been suggested for achieving high track density as a possible solution. Dual-loop servo system is generally classified into a two-input-two-output system, but if we use an estimator for a two-input-two-output system, it can be converted into two input one output system. Since we can't control the dual stage servo system by the classical method, it requires a special technique; for example, Parallel Loop System, Master-Slave Loop System, Decoupled Master-Slave Loop System, and Dual Feedback Loop System. In this paper, we performed experimental evaluations of several types of control algorithm. Further experiments will be made in the future.

• Journal of Power Electronics
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• 제16권4호
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• pp.1565-1577
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• 2016

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• 전기학회논문지P
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• 제61권1호
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• pp.5-9
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• 2012

In this paper, multi folded dual monopole antenna for WLAN communication of dual bend is designed and fabricated. The proposed multi folded dual monopole antenna are consisted of two folded rectangle loops by microstrip fed that is modified dual monopole antenna. Therefore, the outside rectangle loop structure of the proposed antenna is extended a dual monopole. The characteristics of the proposed antenna is analyzed return loss and radiation patterns by the FDTD tools. As a result a bandwidth of proposed antenna has about 0.82GHz from 2.0 to 2.82[GHz] and 0.7GHz from 5.46 to 6.16[GHz]. It is used WLAN communications of 2[GHz] and 5[GHz].

• 한국자동차공학회논문집
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• 제18권5호
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• pp.136-144
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• 2010

Exhaust gas recirculation (EGR) is an emission control technology allowing significant NOx emission reduction from light-and heavy duty diesel engines. The future EGR type, dual loop EGR, combining features of high pressure loop EGR and low pressure loop EGR, was developed and optimized by using a commercial engine simulation program, GT-POWER. Some variables were selected to control dual loop EGR system such as VGT (Variable Geometry Turbocharger)performance, especially turbo speed, flap valve opening diameter at the exhaust tail pipe, and EGR valve opening diameter. Applying the dual loop EGR system in the light-duty diesel engine might cause some problems, such as decrease of engine performance and increase of brake specific fuel consumption (BSFC). So proper EGR rate (or mass flow) control would be needed because there are trade-offs of two types of the EGR (HPL and LPL) features. In this study, a diesel engine under dual loop EGR system was optimized by using design of experiment (DoE). Some dominant variables were determined which had effects on torque, BSFC, NOx, and EGR rate. As a result, optimization was performed to compensate the torque and BSFC by controlling start of injection (SOI), injection mass and EGR valves, etc.

• 대한전자공학회논문지SD
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• 제45권5호
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• pp.82-87
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• 2008

본 논문은 고속 위상 고정이 가능한 새로운 듀얼 슬로프 위상고정루프를 제안한다. 기존의 듀얼 슬로프 위상고정루프는 각각 2개의 전하펌프와 위상 주파수 검출기로 구성되었다. 본 논문에서는 위상차에 따라 전하펌프의 전류를 조절해 하나의 전하펌프와 위상 주파수 검출기만으로 듀얼 슬로프 위상고정루프를 구현하였다. 제안된 회로는 $0.35{\mu}m$ CMOS 공정 파라미터 값으로 HSPICE 시뮬레이션을 수행하여 회로의 동작을 검증하였다. 제안된 듀얼 슬로프 위상고정루프의 위상 고정 시간은 $2.2{\mu}s$로 단일 슬로프 위상고정루프의 위상 고정 시간인 $7{\mu}s$보다 개선된 결과를 얻었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1991년도 추계학술대회 논문집 학회본부
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• pp.175-178
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• 1991

The drive system of servo motor is requested to have robustness of disturbance and parameter variation. However, the dynamics of PMSM drive change significantly by forced disturbance and parameter variation. Moreover, the state error caused by them should be suppressed completely and rapidly. In this paper, the vector-control system of PMSM using dual adaptive control loop is investigated. In the proposed system, linear adaptive control loop rapidly recovers the state error caused by both disturbance and parameter variation. In the dual adaptive control loop, the inner loop reduces the system sensitivity of parameter variation and disturbance, and the outer loop suppresses the state error caused by them completely. The proposed servo system is verified through a computer simulations and experimental results.