• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.11
• /
• pp.698-703
• /
• 2015

In this study, we fabricated the dual gate (DG) ion-sensitive field-effect-transistor (ISFET) with flexible polyimide (PI) extended gate (EG). The DG ISFETs significantly enhanced the sensitivity of pH in electrolytes from 60 mV/pH to 1152.17 mV/pH and effectively improved the drift and hysteresis phenomenon. This is attributed to the capacitive coupling effect between top gate and bottom gate insulators of the channel in silicon-on-transistor (SOI) metal-oxide-semiconductor (MOS) FETs. Accordingly, it is expected that the PI-EG based DG-ISFETs is promising technology for high-performance flexible biosensor applications.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.53 no.7
• /
• pp.358-363
• /
• 2004

A new 600 V dual gate transistor employing thyristor action, which incorporates floating PN junction and trench gate IGBT, is proposed to improve the forward current-voltage characteristics and the short circuit ruggedness. Our two-dimensional numerical simulation shows that the proposed device exhibits low forward voltage drop and eliminates the snapback phenomena compared with conventional trench gate IGBT and EST The proposed device achieves high current saturation characteristics by separating floating N+ emitter and cathode. The proposed device achieves low saturation current value compared with conventional devices, and the short-circuit ruggedness is improved. The proposed device may be suitable for the use of high voltage switching applications.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2018.05a
• /
• pp.171-172
• /
• 2018

Dual gate L-shaped tunnel field-effect-transistor (DG-LTFET) is presented in this study. DG-LTFET achieves near vertical subthreshold slope (SS) and its ON current is also found to be higher then both conventional TFET and LTFET. This device could serve as a potential replacement for conventional complimentary metal-oxide-semiconductor (CMOS) technology.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.6
• /
• pp.208-211
• /
• 1997

We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.54 no.1
• /
• pp.18-22
• /
• 2005

We have proposed and fabricated a dual gate AlGaN/GaN high electron mobility transistor (HEMT), which exhibits the low leakage current and the high breakdown voltage for the high voltage switching applications. The additional gate between the main gate and the drain is specially designed in order to decrease the electric field concentration at the drain-side of the main gate. The leakage current of the proposed HEMT is decreased considerably and the breakdown voltage increases without sacrificing any other electric characteristics such as the transconductance and the drain current. The experimental results show that the breakdown voltage and the leakage current of proposed HEMT are 362 V and 75 nA while those of the conventional HEMT are 196 V and 428 nA, respectively.

• Proceedings of the KIEE Conference
• /
• 2001.07c
• /
• pp.1469-1471
• /
• 2001

A Dual Channel Trench IGBT (Insulated Gate Bipolar Transistor) is proposed to improve the latch-up characteristics. Simulation results by MEDICI have shown that the latching current density of proposed device was found to be 2850 A/$cm^2$ while that of conventional device was 1610 A/$cm^2$. The latching current desity of the proposed strucutre was 77.02% higher than that of conventional structre.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.27 no.2
• /
• pp.76-80
• /
• 2014

Dual-gate PCRAM which unify capacitor-less DRAM and NVM using a PCM instead of a typical SONOS flash memory is proposed as 1 transistor. $VO_2$ changes its phase between insulator and metal states by temperature and field. The front-gate and back-gate control NVM and DRAM, respectively. The feasibility of URAM is investigated through simulation using c-interpreter and finite element analysis. Threshold voltage of NVM is 0.5 V that is based on measured results from previous fabricated 1TPCM with $VO_2$. Current sensing margin of DRAM is 3 ${\mu}A$. PCM does not interfere with DRAM in the memory characteristics unlike SONOS NVM. This novel unified dual-gate PCRAM reported in this work has 1 transistor, a low RESET/SET voltage, a fast write/erase time and a small cell so that it could be suitable for future production of URAM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.4
• /
• pp.296-299
• /
• 2008

The effects of radio frequency (RF) source power for decoupled plasma nitridation (DPN) process on the electrical properties and Fowler-Nordheim (FN) stress immunity of the oxynitride gate dielectrics for deep nano-technology devices has been investigated. With increase of RF source power, the threshold voltage (Vth) of a NMOS transistor(TR) decreased and that of a PMOS transistor increased, indicating that the increase of nitrogen incorporation in the oxynitride layer due to higher RF source power induced more positive fixed charges. The improved off-current characteristics and wafer uniformity of PMOS Vth were observed with higher RF source power. FN stress immunity, however, has been degenerated with increasing RF source power, which was attributed to the increased trap sites in the oxynitride layer. With the experimental results, we could optimize the DPN process minimizing the power consumption of a device and satisfying the gate oxide reliability.

• Journal of the Korea Computer Industry Society
• /
• v.6 no.5
• /
• pp.783-790
• /
• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• Transactions on Electrical and Electronic Materials
• /
• v.16 no.5
• /
• pp.254-259
• /
• 2015

This paper reports the optimized mixed-signal performance of a high-voltage (HV) laterally double-diffused metaloxide-semiconductor (LDMOS) field-effect transistor (FET) with a dual gate oxide (DGOX). The fabricated device is based on the split-gate FET concept. In addition, the gate oxide on the source-side channel is thicker than that on the drain-side channel. The experiment results showed that the electrical characteristics are strongly dependent on the source-side channel length with a thick gate oxide. The digital and analog performances according to the source-side channel length of the DGOX LDMOS device were examined for circuit applications. The HV DGOX device with various source-side channel lengths showed reduced by maximum 37% on-resistance (R_ON) and 50% drain conductance (g_ds). Therefore, the optimized mixed-signal performance of the HV DGOX device can be obtained when the source-side channel length with a thick gate oxide is shorter than half of the channel length.