• 전자공학회논문지SC
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• 제39권2호
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• pp.140-145
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• 2002

본 논문은 단락회로 전류를 없애기 위한 CMOS 버퍼회로에 대한 것이다. 최종 구동소자는 풀-업 PMOS와 풀-다운 NMOS로 구성하고 이를 구동하기 위해 두가지 경로를 입력신호로 선택되도록 하였다. 이러한 기법으로 최종 구동회로가 짧은 시간동안 tri-state가 되어 단락회로 전류를 차단하였다. 모의 실험결과 전원전압 3.3V에서 전력-지연 곱을 기존의 Tapered 버퍼[1]와 비교하여 약 42% 줄일 수 있었다

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.287-289
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• 2011

본 논문은 인피니언 테크놀로지스의 RC-IGBT (Reverse Conducting Isolated Gate Bipolar Transistor)와 SOI 드라이브 IC(Integrated Circuit)를 사용한 DIL(Dual-In-Line) 구조의 저전력 모듈인 CIPOS TM (Control Integrated POwer System) 제품을 소개한다. 이 전력 모듈은 최적의 게이트 구동회로, 트렌치 필드스톱의 RC-IGBT를 사용하여 기존의 IGBT 와 Diode를 사용하는 구조에서 최소화 된 패키지 크기를 사용하여 높은 효율을 구현할 수 있다. 본 논문을 통하여 인버터의 어플리케이션에 적합하게 설계된 전력모듈에 대한 소개와 그 특징 및 시스템 구성을 위한 고려사항에 대하여 기술하였다.

• 전자공학회논문지D
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• 제35D권5호
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• pp.1-10
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• 1998

A GaAs MMIC composed of VCO (voltage controlled oscillator) and mixer for PCS receiver has been developed using 1.mu.m ion implanted GaAs MESFET process. The VCO consists of a colpitts-type oscillator with a dielectric resonator and the circuit configuration of the mixer is a dual-gate type with an asymmetric combination of LO and RF FETs for the improvement of intermodulation characteristics. The common-source self-biasing is used in all circuits including a buffer amplifier and mixer, achieving a single power supply (3V) operation. The total power dissipation is 78mW. The VCO chip shows a phase noise of-99 dBc/Hz at 100KHz offset. The combined VCO/mixer chip shows a flat conversion gain of 2dB, the frequency-tuning factor of 80MHz/volts in the varacter bias ranging from 0.5V to 0.5V , and output IP3 of dBm at varactor bias of 0V. The fabricated chip size is 2.5mm X 1.4mm.

• 전자공학회논문지D
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• 제34D권10호
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• pp.14-23
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• 1997

An MMIC downconverting mixer for cellular phone application has been successfully developed using an MMIC process including $1 \mu\textrm{m}$ ion implanted gaAs MESFET and passive lumped elements consisting of spiral inductor, $Si_3N_4$ MIM capacitor and NiCr resistor. The configuration of the mixer presented in this paper is single-ended dual-gate FET mixer with common-source self-bias circuits for single power supply operation. The dimension of the fabricated circuit is $1.4 mm \times 1.03 mm $ including all input matching circuits and a mixing circuit. The conversion gian and noise figure of the mixer at LO powr of 0 dBm are 5.5dB and 19dB, respectively. The two-tone IM3 characteristics are also measured, showing -60dBc at RF power of -30dBm. Allisolations between each port show better than 20dB.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1343-1345
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• 2001

본 논문은 스냅백을 효과적으로 제거하고 순방향 전압 강하를 줄이는 새로운 구조의 분리된 이중 게이트 SOI SA-LIGBT를 제안하였다. 제안된 소자는 분리된 단락 애노드와 플로팅 오믹 접합의 적용을 통해 스냅백이 성공적으로 제거되었고, 순방향전압강하는 전류밀도가 100A/$cm^2$일 때 기존의 SA-LIGBT에 비교해서 2V 감소된다. 또한 턴-오프 특성도 분리된 단락 애노드를 적용하였기 때문에 SA-LIGBT보다 개선되었다.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2008년도 춘계학술대회 논문집
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• pp.325-328
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• 2008

This paper presents a new conceptual electromagnetic induction eddy current-based stainless steel plate spiral type heater for heat exchanger or dual packs Heater in hot water system boiler steamer and super heated steamer, which is more suitable and acceptable for new generation consumer power applications. In addition, an active clamped quasi resonant PWM high frequency inverter using trench gate IGBTs power module can operate under a principle of zero voltage soft commutation with PWM is developed and demonstrated fora high efficient induction heated hot water system and boiler in the consumer power applications This consumer induction heater power appliance using active clamp soft switching PWM high-frequency inverter is evaluated and discussed on the basis of the simulation and experimental results.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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• pp.71-74
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• 2003

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improve the snap-back effect which leads to a lot of problem of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor(EST) with trench electrode has been proposed for improving snap-back effect. It is observed that the forward blocking voltage of the proposed device is 800V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrode, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.232-234
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• 2002

Due to development of power electronics technology, power conversion system are tend to small size, easy to use and light weight. Especially motor control system have increased concerns and interests about IPM(Intelligent Power Module) inverter, which contains protection circuit, drive circuit and power devices. So, we manufactured 3-phase inverter using DIP-IPM(Dual in-line package IPM) PS21245- E(1.5 Kw) made by MITSUBISHI Electric. Some of these features include -HVIC to Provide level shifting and gate drive for high-side IGBTs. The interface circuit between pwm controller and DIP-IPM can made by direct connection. In order to validate dynamic performance of the proposed system, the actual experiment worked out at wide speed range. The developed system is shown as a good dynamic characteristics.

• Transactions on Electrical and Electronic Materials
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• 제2권3호
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• pp.33-37
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• 2001

A vertical trench electrode type EST has been proposed in this paper. The proposed device considerably improves snapback which leads to a lot of problems of device applications. In this paper, the vertical dual gate Emitter Switched Thyristor (EST) with trench electrode has been proposed for improving snab-back effect. It is observed that the forward blocking voltage of the proposed device is 745V. The conventional EST of the same size were no more than 633V. Because the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and the punch through breakdown of the proposed EST is occurred at latest.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.1063-1066
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• 2000

ln this paper, a new active phase shifter is proposed using a vector sum method, and it is shown that the proposed phase shifter is more efficient than the others in size, power, number of circuits, and gain. Also a unique digital phase control method of the circuit is suggested. The proposed scheme was designed and implemented using a Wilkinson power combiner/divider, a branch line 3dB quadrature hybrid coupler and variable gain amplifiers (VGAs) using dual gate FETs (DGFETs). Furthermore, it is also shown that the proposed scheme is more efficient and works properly with the digital phase control method.