• Korean Management Science Review
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• v.16 no.1
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• pp.1-9
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• 1999

The purpose of this paper is to develope efficient techniques for implementing the dual simplex method. In this paper we proposed one artificial row technique to get an initial dual feasible basic solution, a dual steepest-edge method coupled with a dropping row selection rule, and an anti-degeneracy technique which resembles the EXPAND procedure for the primal simplex method. The efficiency of the above techniques is shown by experiments. Finally, the dual simplex method is shown to be superior to the primal simplex method when it is used in the integer programming.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.05a
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• pp.546-550
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• 2003

For dual-band operation, it can be done by loading two pair of narrow slots in the equilateral-triangular patch, one embedded close to the side edges of the patch and the other inserted at the bottom edge of the patch. The obtained two operating frequencies are of same polarization planes. The frequency ratio of the two operating frequencies is turnabled by varing the positions and lengths of the inserted slots at the bottom edge of the patch. In this paper, A single-feed equilateral-triangular microstrip patch with two pairs of narrow slot for dual-frequency operation is printed on the substrate(TMN-4 Rosers Co.) of the 60 miles. the antenna radiation characteristics are calculated by Ensemble ver. 5.0 software, and compared with the experimental results.

• The Journal of Korea Robotics Society
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• v.9 no.3
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• pp.140-146
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• 2014

This paper introduces a dual-arm robot painter system which is capable of sketching a camera-captured image with short line segments. To express various curved edges in the image by combining line segments, we first apply edge detection algorithm to the entire image, split the edged image into small boxed pieces, and then apply Hough Transformation to each piece so that the edges inside the piece can be approximated with short line segments. To draw the picture within a reasonable time, we designed a simple dual-arm robot system and controlled both arms concurrently according to linear interpolation algorithm. From the experiments, we could verify that simple linear motions can describe various images effectively with a unique brush style.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.275-278
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• 1999

In this paper, Dual PFD(Phase Frequency Detector) with improved phase locking time is proposed. The proposed PFD consists of positive and negative edge triggered D flip-flop. In order to confirm the characteristics of proposed PFD, HSPICE simulations are performed using a 0.25${\mu}{\textrm}{m}$ CMOS process. As a result of simulations, the proposed PFD has a characteristic of fast phase locking time with dead zone free.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.1-4
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• 2009

This work shows how the adoption of a dual-dicing process for silicon wafer separation affects the thermal-cycling reliability (i.e. $-65^{\circ}C$ to $150^{\circ}C$) of the semiconductor devices utilizing lead-on-chip (LOC) die attach technique. In-situ examinations show that conventional single-dicing process directly attacks the edge region of diced devices but dual-dicing process effectively protects the edge region of diced devices from dicing-induced mechanical damage. Probably, this is because the preferential and sacrificial fracture of notched regions induced on the active surface of wafers saves the edge regions. It was also investigated through thermal-cycling tests that the number of thermal-cycling induced failures is much lower at the dual-dicing process than the single-dicing process.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.39 no.1
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• pp.16-21
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• 2002

In this paper, a dual type PFD(Phase Frequency Detector) for high speed PLL to improve output characteristics using TSPC(True Single Phase Clocking) circuit is proposed. The conventional 3-state PFD has problems with large dead-zone and long delay time. Therefore, it is not applicable to high-speed PLL(Phase-Locked Loop). A dynamic PFD with dynamic CMOS logic circuit is proposed to improve these problems. But, it has the disadvantage of jitter noise due to the variation of the duty cycle. In order to solve the problems of previous PFD, the proposed PFD improves not only the dead zone and duty cycle but also jitter noise and response characteristics by the TSPC circuit and dual structured PFD circuit. The PFD is consists of a P-PFD(Positive edge triggered PFD) and a N-PFD(Negative edge triggered PFD) and improves response characteristics to increase PFD gain. The Hspice simulation is performed to evaluate the performance of proposed PFD. From the experimental results, it has the better dead zone, duty cycle and response characteristics than conventional PFDs.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.182-189
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• 2014

A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.8
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• pp.1139-1145
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• 2002

Wavelet transformed data can filter signal with each frequency band, because it includes detail information about original signal. Therefore, in this paper, important two noises were removed by wavelet. About AWGN environment UDWT(undecimated discrete wavelet transform), applying hard-threshold, was used and about impulse noise environment, it can be possible to recognize edge of original signal as well as superior denoising effect by using two methods, denoising by threshold and slope of signal by wavelet. SNR was used as a judgemental criterion of a denoising effect and Blocks and DTMF(dual tone multi frequency) were used as a test signal.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.127-127
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• 2010

Owing to many advantages on indirect intersubband absorption from the hole miniband to the electron miniband based on the type-II band alignment in InAs/GaSb strained-layer superlattice (SLS), InAs/GaSb SLS infrared photodetector (SLIP) has emerged as a promising system to realize high-detectivity quantum photodetector operating up to room temperature in the spectral range of mid-infrared (MIR) to far-infrared (FIR). In particular, n-barrier-n (n-B-n) structure designed for blocking the majority-carrier dark current makes it possible for MIR/FIR dual-band SLIP whose photoresponse (PR) band can be exclusively selected by the bias polarity. In this study, we present the MIR and FIR photoresponse (PR) mechanism identified by dual-band PR spectra and photoluminescence (PL) profiles taken from InAs/GaSb SLIP. In the MIR/FIR PR spectra measured by changing bias polarity, each spectrum individually shows a series of distinctive peaks related to the transitions from the hole subbands to the conduction one. The PR mechanism at each polarity is discussed in terms of diffusion current, and a superposition of MIR-PR in the FIR-PR spectrum is explained by tunnelling of electrons activated in MIR-SLS. The effective FIR-PR spectrum decomposed into three curves for HH1, LH1, and HH2 has revealed the edge energies of 120, 170, and 220 meV, respectively, and the temperature variation of the MIR-PR edge energies shows that the temperature behavior of the SLS systems can be approximately expressed by the Varshni empirical equation.