• 한국정보통신학회논문지
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• 제25권11호
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• pp.1627-1634
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• 2021

본 논문은 저전력 뉴럴 네트워크 가속기 SOC를 위한 아날로그 Convolution Filter용 저전력 초소형 ADC 회로 및 칩 설계 기술을 소개한다. 대부분의 딥러닝의 학습과 추론을 할 수 있는 Convolution neural network accelerator는 디지털회로로 구현되고 있다. 이들은 수많은 곱셈기 및 덧셈기를 병렬 구조로 구현하며, 기존의 복잡한 곱셉기와 덧셈기의 디지털 구현 방식은 높은 전력소모와 큰 면적을 요구하는 문제점을 가지고 있다. 이 한계점을 극복하고자 본 연구는 디지털 Convolution filter circuit을 Analog multiplier와 Accumulator, ADC로 구성된 Analog Convolution Filter로 대체한다. 본 논문에서는 최소의 칩면적와 전력소모로 Analog Accumulator의 아날로그 결과 신호를 디지털 Feature 데이터로 변환하는 8-bit SAR ADC를 제안한다. 제안하는 ADC는 Capacitor Array의 모든 Capacitor branch에 Split capacitor를 삽입하여 모든 branch의 Capacitor 크기가 균등하게 Unit capacitor가 되도록 설계하여 칩면적을 최소화 한다. 또한 초소형 unit capacitor의 Voltage-dependent capacitance variation 문제점을 제거하기 Flipped Dual-Capacitor 회로를 제안한다. 제안하는 ADC를 TSMC CMOS 65nm 공정을 이용하여 설계하였으며, 전체 chip size는 1355.7㎛², Power consumption은 2.6㎼, SNDR은 44.19dB, ENOB는 7.04bit의 성능을 달성하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.333-336
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• 2002

An alternative CMOS implementation of a multi-output four-terminal floating nullor (FTFN) with constant-g$_{m}$ rall-to-rail input stage is proposed. This presented circuit is based on the advantages of a complementary transconductance amplifier and class AB dual translinear cell circuit that comes up with wide bandwidth. The constant-g$_{m}$ characteristic is controlled by the maximum-current selection circuits, maintaining the smooth response over the change of input common mode voltage. The circuit performances are confirmed through HSPICE simulations. A current-mode multifunction filter is used to exhibit the potentiality of this proposed scheme.eme.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1660-1661
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• 2011

본 논문에서는 7중 대역 (GSM850, GSM900, DCS1800, PCS1900, UMTS850, UMTS1900, UMTS2100) 을 지원하는 LPF 내장형 LTCC 프런트 엔드 모듈 (FEM) 을 설계, 제작 및 측정하였다. 제작된 FEM은 효과적인 고조파 제거를 위해 수동소자를 LTCC 기판에 내장하여 저역 통과 필터(LPF)를 구현하였다. 본 논문에서 제안하는 FEM은 송수신 신호를 선택하기 위한 flip-chip 형태의 CMOS RF SP9T switch, Rx 신호의 수신을 위한 dual type의 SAW filter, 매칭 및 ESD 보호 회로를 위한 0603 크기의 칩소자가 부품 외부에 실장되어 구현된다. 전체 크기는 $4.5{\times}3.2{\times}1.2\;mm^3$의 초소형으로 내부 GND 2개 층을 포함하여 총 16층으로 구성된다. 측정결과는 송신단과 수신단의 삽입손실이 각각 1.7 dB, 3.6 dB 이하의 우수한 특성을 보였다.

• 한국음향학회:학술대회논문집
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• 한국음향학회 2004년도 추계학술발표대회논문집 제23권 2호
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• pp.283-286
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• 2004

Due to advances in electronics very high quality audio reproduction is today possible. But the listening environment causes deviation of the audio system from the expected behavior. Firstly the listening Room significantly changes the audio signal frequencies and their phase. Secondly the position of the user in the room affects the perceived sound. With existing DSP technology it is possible to adequately correct these effects. In our work we developed a room correction system, correcting up to 7.1 channels using dual Motorola 56367 fixed point DSP's, implementing position dependent room effects measurement, real time compensation filter design and equalization filtering procedures.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1603_1604
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• 2009

본 논문에서는 SIR(Stepped Impedance Resonator)를 이용하여 RFID 주파수 대역의 이중대역 필터를 설계 연구하였다. 반파장 SIR을 parallel-coupled 형태로 설계하고 넓은 주파수 간격의 이중대역필터를 구현하기 위해서 2st 공진 주파수를 2.45GHz 대역에 맞추고 1st 공진 주파수를 억제하기 위해서 대역저지 필터를 결합하였다. 입출력에 대역 저지 필터를 구성하고 반파장 parallel-coulpled SIR은 미앤더 구조로 설계하여 크기를 줄였다. 본 논문에서 설계된 필터는 두 대역에서 -3.5~3.9dB의 삽입 손실을 가지며 433MHz에서 8MHz, 2.45GHz에서 21MHz의 대역폭을 나타낸다. 관심 주파수 이외의 대역에서는 -50dB 이상의 저지 특성을 가진다.

• 한국전기전자재료학회논문지
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• 제19권4호
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• pp.328-333
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• 2006

In this paper, we developed a pressure measurement apparatus with the parallel structure to improve the measurement efficiency of pressure sensors by reducing the measurement time of pressure. The developed system has two parallel positions for loading Silicon pressure sensor and has a dual valve structure. The semiconductor pressure sensors prepared by Copal Electronics were used to confirm the performance of the developed measurement system. Two stage differential amplifier circuit was employed to amplify the weak output signal and the amplified output signal was improved utilizing a low-pass filter. New apparatus shows the measurement time of pressure two times shorter than that of conventional one with the serial structure, while both structures show the similar linear output versus pressure characteristics.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2311-2318
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• 2005

Progress in the LCD industries has been very rapid. Therefore, their manufacturing lines require larger LCD glass-handling robots and more precise path control of the robots. In this paper, we present two practical advanced algorithms for high-precision path generation of an LCD glass-handling robot. One is high-precision path interpolation for continuous motion, which connects several single motions and is a reliable solution for a short robot cycle time. We demonstrate that the proposed algorithm can reduce path error by approximately 91% compared with existing algorithms without increasing cycle time. The second is real-time static deflection compensation, which can optimally compensate the static deflection of the handling robot without any additional sensors, measurement instruments or mechanical axes. This reduces vertical path error to approximately 60% of the existing system error. All of these algorithms have been commercialized and applied to a seventh-generation LCD glass-handling robot.

• 전자공학회논문지A
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• 제33A권10호
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• pp.115-122
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• 1996

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

• 전자공학회논문지A
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• 제32A권6호
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• pp.787-798
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• 1995

We implement the E-plane T-juncition manifold mutiplexer having low insertion loss for output multiplexer of Ku-band satellite transponder. Manifold multiplexer implemented here is composed of 2 channel filters, T-junctions, half-wave waveguide connecting channel filters and manifold, and manifold itself.[1-4] Considering the mass and volume of the satellite transponder, the channel filters are designed to dual-mode.[5-13] And Elliptic filter function is used, which has good characteristics of suppressing the interference between 2 channels. Since the performance of manifold multiplexer depends on the manifold waveguide transmission line length, it's necessary proper analysis. In this paper, we do optimization process of T-junction and other elements by using CAD and implement the manifold multiplexer. An experiment shows that characteristic response of multiplexer matches wel its modeling result.