• The Transactions of the Korean Institute of Electrical Engineers P
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• v.62 no.2
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• pp.84-89
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• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.141-148
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• 2006

In this study, the design of advanced LVDS(Low Voltage Differential Signaling) I/O interface circuit with new structural low triggering ESD (Electro-Static Discharge) protection circuit was investigated. Due to the differential transmission technique and low signal swing range, maximum transmission data ratio of designed LVDS transmitter was simulated to 5Gbps. And Zener Triggered SCR devices to protect the ESD Phenomenon were designed. This structure reduces the trigger voltage by making the zener junction between the lateral PNP and base of lateral NPN in SCR structure. The triggering voltage was simulated to 5.8V. Finally, The high speed I/O interface circuit with the low triggered ESD protection device in one-chip was designed.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.212-222
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• 1992

To use polycrystalline Si Thin Film Transistor (poly-Si TFT) in high density SRAM instead of High Load Resistor (HLR), TFT is needed to show good electrical characteristics such as large carrier mobility, low leakage current, high driver current and low subthreshold swing. To satisfy these electrical characteristics, the trap state density must be reduced in the channel poly. Technological issues pertinent to the channel poly fabrication process are investigated and discussed. They are solid phase growth (SPG), Si-ion implantation, laser annealing and hydrogenation. The electrical properties of several CVD oxides used as the gate oxide of TFT are compared. The dependence of the electrical characteristics of TFT on source-drain ion-implantation dose, drain offset length and dopant lateral diffusion are also described.

• ETRI Journal
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• v.30 no.4
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• pp.612-614
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• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• Journal of Power System Engineering
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• v.6 no.4
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• pp.81-87
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• 2002

The modelling and controller design of the EMV(electro-magnetic valve) for vehicle engine are considered in this paper. For the analysis and controller design, the governing equation of the EMV system is derived. For a good performance of the system, the start control, the holding control and the swing control are included in the controller design of the EMV system. In order to reduce landing speed of the valve, the on-time delay control which mainly come from the optimal control theory is employed. In order to reduce the power consumption of the system, the pick-up and hold operation has been used for the magnetic coil. The simulation and experimental results are presented to show the validity of the control method.

• Korean Journal of Applied Biomechanics
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• v.15 no.4
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• pp.181-189
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• 2005

To know the proper impact posture and changes for the various clubs, changes of impact variables according to the change of golf club length was investigated. Swing motions of three male low handicappers including a professional were taken using two high-speed video cameras. Four clubs iron 7, iron 5, iron 3 and driver (wood 1) were selected for this experiment. Three dimensional motion analysis techniques were used to get the kinematical variables. Mathcad and Kwon3D motion analysis program were used to analyze the position, distance and angle data in three dimensions. Major findings of this study were as follows. 1. Lateral position of the head remained more right side of the target up to 3.5cm compared to the setup as the length of the club increased. 2. Left shoulder raised up to 5cm and right shoulder lowered up to 2.5cm compared to setup. The shoulder line opened slightly (maximum 11 degrees) to the target line. 3. Forward lean angle of the trunk decreased up to 4 degrees (more erected) compared to setup. 4. Side lean angle of the trunk increased compared to setup and increased up to 16 degrees as the club length increased. 5. The pelvis moved to the target line direction horizontally and opened up to 31 degrees. Right hip moves laterally to the grip position at the setup. 6. Flexion of the left leg maintained almost constantly but the right leg flexed up to 11 degrees compared to setup. 7. Left arm is straightened but the right arm flexed about 20degrees compared to straight. 8. Center of the shoulders were in front of the knees and toes of the feet. 9. Hands moved to the left (8.7cm), forward (5.7cm) and upward (11.6cm) compared to the setup. This is because of the rotation of pelvis and shoulders. 10. Shaft angle to the ground was smaller than the lie angle of the clubs but it increased close to the lie of the clubs at impact.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.1
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• pp.110-116
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• 2016

This paper describes 1.2-V 5-Gb/s scalable low voltage signaling(SLVS) differential transmitter(TX) with a digital impedance calibration and equalizer. The proposed transmitter consists of a phase-locked loop(PLL) with 4-phase output clock, a 4-to-1 serializer, a regulator, an output driver, and an equalizer driver for improvement of the signal integrity. A pseudo random bit sequence generator is implemented for a built-in self-test. The proposed SLVS transmitter provides the output differential swing level from 80mV to 500mV. The proposed SLVS transmitter is implemented by using a 65-nm CMOS with a 1.2-V supply. The measured peak-to-peak time jitter of the implemented SLVS TX is about 46.67 ps at the data rate of 5Gb/s. Its power consumption is 1.88 mW/Gb/s.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.52-58
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• 2006

Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.21-32
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• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.