• 한국지반신소재학회논문집
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• 제9권2호
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• pp.11-20
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• 2010

본 연구에서는 국내에서 사용하고 있는 연직배수재의 통수능시험 평가방법과 국내 관련 시방기준들을 고찰하고 연직배수재통수능 시험시 결과에 영향을 미치는 인자로 동수경사 변화에 따른연직배수재의 통수능 시험 결과를 분석하였다. 국내 연직배수재의 통수능 평가시험방법으로 기존 Delft 방법에 근거한 KS K 0940(2008)이 최근 한국표준으로 등재되었으며, 이 시험방법을 사용하는 경우 동수경사의 변화에 따라 연직배수재의 통수능의 차이가 크게 나타날 가능성이 있는 것으로 확인되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.46-52
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• 2012

Separate extraction of source ($R_S$) and drain ($R_D$) resistances caused by process, layout variations and long term degradation is very important in modeling and characterization of MOSFETs. In this work, we propose "Avalanche Hot-Source Method (AHSM)" for simple separated extraction of $R_S$ and $R_D$ in a single device. In AHSM, the high field region near the drain works as a new source for abundant carriers governing the current-voltage relationship in the MOSFET at high drain bias. We applied AHSM to n-channel MOSFETs as single-finger type with different channel width/length (W/L) combinations and verified its usefulness in the extraction of $R_S$ and $R_D$. We also confirmed that there is a negligible drift in the threshold voltage ($V_T$) and the subthreshold slope (SSW) even after application of the method to devices under practical conditions.

• 한국전기전자재료학회논문지
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• 제29권2호
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• pp.69-74
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• 2016

In this study, we proposed an a-IGZO (amorphous In-Ga-Zn-O) TFT (thin-film transistor) with off-planed source/drain structure. Furthermore, two different electrode materials (ITO and Ti) were applied to the source and drain contacts for performance improvement of a-IGZO TFTs. When the ITO with a large work-function and the Ti with a small work-function are applied to drain electrode and source contact, respectively, the electrical performances of a-IGZO TFTs were improved; an increased driving current, a decreased leakage current, a high on-off current ratio, and a reduced subthreshold swing. As a result of gate bias stress test at various temperatures, the off-planed S/D a-IGZO TFTs showed a degradation mechanism due to electron trapping and both devices with ITO-drain or Ti-drain electrode revealed an equivalent instability.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.576-580
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• 2013

We investigate the enhanced effects of asymmetry ratio variations of the source and drain area in silicon (Si) field-effect transistor (FET). Photoresponse according to the variation of asymmetry difference between the width of source and drain are obtained by using the plasmonic terahertz (THz) wave detector simulation based on technology computer-aided design (TCAD) with the quasi-plasma 2DEG model. The simulation results demonstrate the potential of Si FETs with asymmetric source and drain structures as the promising plasmonic THz detectors.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.344-345
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• 2012

The Gate-Induced-Drain-Leakage (GIDL) current with channel doping and width dependence are characterized. The GIDL currents are found to increase in MOSFETs with higher channel doping levels and the observed GIDL current is generated by the band-to-band-tunneling (BTBT) of electron through the reverse-biased channel-to-drain p-n junction. A BTBT model is used to fit the measured GIDL currents under different channel-doping levels. Good agreement is obtained between the modeled results and experimental data. The increase of the GIDL current at narrower widths in mainly caused by the stronger gate field at the edge of the shallow trench isolation (STI). As channel width decreases, a larger portion of the GIDL current is generated at the channel-isolation edge. Therefore, the stronger gate field at the channel-isolation edge causes the total unit-width GIDL current to increases for narrow-width devices.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1321-1323
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• 1998

We investigated drain leakage current in GaAs power MESFET. The device we studied by 20 simulation has a $1000{\AA}$ thick AlGaAs buffer layer under n-GaAs active layer. The calculation shows that the leakage current through GaAs substrate is significantly reduced by the buffer layer.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.89-90
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• 2007

In this paper, we propose Doherty amplifier with proper drain bias line. By $\lambda$/4 microstrip line, IMD is eliminated. Also output power of amplifier is reduced in wanted bandwidth. For linearity improvement, we design drain bias with narrow $\lambda$/4 microstrip line. We observe that gain characteristics improve 1dB and $3^{rd}/5^{th}$ IMD characteristics reduce 5dB/10dB.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.42-44
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• 2007

The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

• 한국재난정보학회 논문집
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• 제13권4호
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• pp.483-490
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• 2017

최근 경제성장과 함께 산업용, 주거용 토지의 요구가 증대되고 있으나 좋은 지반조건으로 개발된 토지를 얻기가 어려워지고 있다. 샌드드레인, 모래다짐말뚝, 팩드레인, 프라스틱보드드레인(PBD)등 다양한 연직배수기술이 연약지반의 경제적 개발을 가능하게 하고 있다. 연직배수에서는 통수능력이 중요한 요소이다. 그러나, 현장조건에서는 토질조건, 상재하중 등 다양한 조건에 의하여 통수능력이 변화된다. 본 논문에서는 이중코어형 PBD, 대심도형 PBD, X형 PBD, 일반형 PBD등 4가지 다른 형태의 PBD에 대하여 통수능 시험이 수행되었다. 상재하중과 동수경사에 따른 통수능 특성을 분석하였다. 본 연구에서는 이중코어형의 통수능력이 가장 우수하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.157-157
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• 2008

As the minimum feature size of semiconductor devices scales down to nano-scale regime, ultra shallow junction is highly necessary to suppress short channel effect. At the same time, Ni-silicide has attracted a lot of attention because silicide can improve device performance by reducing the parasitic resistance of source/drain region. Recently, further improvement of device performance by reducing silicide to source/drain region or tuning the work function of silicide closer to the band edge has been studied extensively. Rare earth elements, such as Er and Yb, and Pd or Pt elements are interesting for n-type and p-type devices, respectively, because work function of those materials is closer to the conduction and valance band, respectively. In this paper, we increased the work function between Ni-silicide and source/drain by using Pd stacked structure (Pd/Ni/TiN) for high performance PMOSFET. We demonstrated that it is possible to control the barrier height of Ni-silicide by adjusting the thickness of Pd layer. Therefore, the Ni-silicide using the Pd stacked structure could be applied for high performance PMOSFET.