• Title/Summary/Keyword: Drain engineering

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An Analytical Modeling of Threshold Voltage and Subthreshold Swing on Dual Material Surrounding Gate Nanoscale MOSFETs for High Speed Wireless Communication

  • Balamurugan, N.B.;Sankaranarayanan, K.;Amutha, P.;John, M. Fathima
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.3
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    • pp.221-226
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    • 2008
  • A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

Research on the safety working instructions in the retaining wall construction (concrete retaining wall) (옹벽(콘크리트 옹벽)의 안전작업 지침 개요)

  • Oh, Ki-Taek;Kang, Kyung-Sik
    • Journal of the Korea Safety Management & Science
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    • v.18 no.1
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    • pp.25-33
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    • 2016
  • This guidance purpose is setting Safety Health work instruction for prevent accident such as falling from heights work, collapse and trapped under the heavy equipment and Sediment collapse during retaining wall work by unsder the Industry Safety and Health rules.

Investigation on Contact Resistance of Amorphous Indium Gallium Zinc Oxide Thin Film Transistors with Various Electrodes by Transmission Line Method

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • v.16 no.3
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    • pp.139-141
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    • 2015
  • Contact resistance of interface between the channel layers and various S/D electrodes was investigated by transmission line method. Different electrodes such as Ti/Au, a-IZO, and multilayer of a-IGZO/Ag/a-IGZO were compared in terms of contact resistance, using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes showed good performance and low contact resistance due to the homo-junction with channel layer.

Characteristics of Protein G-modified BioFET

  • Sohn, Young-Soo
    • Journal of Sensor Science and Technology
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    • v.20 no.4
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    • pp.226-229
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    • 2011
  • Label-free detection of biomolecular interactions was performed using BioFET(Biologically sensitive Field-Effect Transistor) and SPR(Surface Plasmon Resonance). Qualitative information on the immobilization of an anti-IgG and antibody-antigen interaction was gained using the SPR analysis system. The BioFET was used to explore the pI value of the protein and to monitor biomolecular interactions which caused an effective charge change at the gate surface resulting in a drain current change. The results show that the BioFET can be a useful monitoring tool for biomolecular interactions and is complimentary to the SPR system.

Balanced Buck-Boost Switching Converter to Reduce Common-Mode Conducted Noise

  • Shoyama Masahito;Ohba Masashi;Ninomiya Tamotsu
    • Proceedings of the KIPE Conference
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    • 2001.10a
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    • pp.212-216
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    • 2001
  • Because conventional switching converters have been usually using unbalanced circuit topologies, parasitic capacitance between the drain/collector of an active switch and the frame ground through its heat sink may generate the common-mode conducted noise. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common-mode conducted noise. As an example, a boost converter version of the balanced switching converter was presented and the mechanism of the common-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switching converter circuit and presents a buck-boost converter version of the balanced switching converter. The feature of common-mode noise reduction is confirmed by experimental results and the mechanism of the common-mode noise reduction is explained using equivalent circuits.

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A New Scaling Theory for the Effective Conducting Path Effect of Dual Material Surrounding Gate Nanoscale MOSFETs

  • Balamurugan, N.B.;Sankaranarayanan, K.;Suguna, M.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.1
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    • pp.92-97
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    • 2008
  • In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

Noise Analysis of Sub Quarter Micrometer AlGaN/GaN Microwave Power HEMT

  • Tyagi, Rajesh K.;Ahlawat, Anil;Pandey, Manoj;Pandey, Sujata
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.3
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    • pp.125-135
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    • 2009
  • An analytical 2-dimensional model to explain the small signal and noise properties of an AlGaN/GaN modulation doped field effect transistor has been developed. The model is based on the solution of two-dimensional Poisson's equation. The developed model explains the influence of Noise in ohmic region (Johnson noise or Thermal noise) as well as in saturated region (spontaneous generation of dipole layers in the saturated region). Small signal parameters are obtained and are used to calculate the different noise parameters. All the results have been compared with the experimental data and show an excellent agreement and the validity of our model.

a-Si Gate Driver with Alternating Gate Bias to Pull-Down TFTs

  • Kim, Byeong-Hoon;Pi, Jae-Eun;Oh, Min-Woo;Tao, Ren;Oh, Hwan-Sool;Park, Kee-Chan
    • 한국정보디스플레이학회:학술대회논문집
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    • 2009.10a
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    • pp.1243-1246
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    • 2009
  • A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

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A Study On The Optimized Process Condition and Current Drivability for Asymmetric Source/Drain SOI Device (비대칭 SOI 소자의 최적화된 공정 조건과 전류구동능력에 관한 연구)

  • Lee, Won-Seok;Chung, Seoung-Ju;Song, Young-Du;Ko, Bong-Gyun;Kwak, Kae-Dal
    • Proceedings of the KIEE Conference
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    • 1999.07d
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    • pp.1671-1673
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    • 1999
  • 일반적으로 SOI 소자에 대한 연구는 film 두께. 채널길이 그리고 doping 농도에 따라 폭넓게 연구되어 왔다. 제안한 소스/드레인 비대칭 SOI 소자는 일반적인 LDD SOI 소자와 비교하여 항복전압은 거의 비슷한 반면. 전류 구동능력은 훨씬향상된 소자를 구현 시킬수 있었다. 비대칭 SOI 소자를 설계하기 위하여 최적화된 공정조건을 모의 실험용 TCAD Simulator (SILVACO)를 이용하여 검증하였다. 검증된 공정 변수를 이용하여 모의 실험을 해보았더니 항복전압과 전류 구동능력에서 좋은 특성을 나타내었다.

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Mathematical Model of Temperature Dependent Characteristics of a-si:H Thin Film Transistor (비정질 실리콘 박막 트랜지스터(a-si:HTFT)의 온도의존특성의 수학적인 해석과 모델)

  • Lee, Woo-Sun;Yoon, Sung-Do;Kang, Yong-Chul;Yoo, Byung-Soo;Lee, Sang-Il
    • Proceedings of the KIEE Conference
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    • 1991.07a
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    • pp.158-161
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    • 1991
  • A new analytical expression for the temperature variation characteristics of hydrogenerated amorphous silicon (a-si:H) thin film transistors, between 223K and 433K, is presented and experimentally virified. The result show that the experimental transfer and output characteristics at several temperatures are easily modeled between $-50^{\circ}C\;and\;90^{\circ}C$. The model is based on three function obtained from the experimental data of $I_D$ versus $V_G$. Theoretical results comfirm the simple form of the model in terms of the device geometry. It was determined that as the temperature increaseed, the saturated drain current increased.

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