• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.630-637
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• 2003

In this paper, a DBM(double balanced mixer) of 2 GHz is implemented on FR4(h=1.6mm, ${\epsilon}_r=4.6$) substrate. The structure of double balanced mixer requires, in general, two talons and a quad diode. For balun, a novel planar balun using microstrip to CPS(Coplanar Strip) is suggested and designed. The suggested balun shows the phase imbalance of $180^{\circ}{\pm}1.5^{\circ}$ and the amplitude imbalance of ${\pm}0.2 dB$ for 1.5 to 2.5 GHz. Using the balun, DBM is successfully implemented, and the measured conversion loss of up/down converter show about 6 dB over the bandwidth. The balun may be applicable for MMIC(Monolithic Microwave Integrated Circuit) DBM with the process supporting backside via though more study.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.988-989
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• 2015

본 논문은 저압 직류배전의 시스템에 적용하기 위한 ZVS 방식의 100kW 고강압 DC-DC 컨버터를 제안하고 실험을 통하여 타당성을 검증하였다. 제안된 시스템은 저압 직류배전 설비에 구성되는 시스템으로 1500Vdc가 송전될 때 가정이나 공업용으로 사용 가능한 380Vdc로 강압시켜주는 장치이다. 고압 특성상 하드 스위칭시 손실이 커 ZVS 동작이 가능하도록 구성하였고, 구성된 시스템에 대해 정격 실험 결과 100kW 부하에서 95.8%의 효율을 보였다.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.124-128
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• 2002

This Paper propose a novel sensorless drive system for the trapezoidal brushless DC motor in Bow speed region. The inverter DC input voltage is controlled by step-down converter for low speed operation. A indirect rotor position sensing technique based on a detailed analysis of the terminal voltage characterisrics is proposed in this paper. A sensorless drive system is implemented using a TMS320F240 for the main process and IPM(Intelligent Power Module) for the inverter.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.218-222
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• 2001

본 논문에서는 B-WLL 상향링크 수신기용 심볼 및 위상 동기 회로를 설계하였다. B-WLL 상향링크는 버스트 전송 방식이고, 변조 방식은 QPSK를 사용한다. 본 연구에서는 심볼율을 2.5 Msymbol/sec로 가정하였고, 디지털 Up/Down Converter를 이용한 IF 대역은 20 [MH]를 사용하였다. 수신필터는 25 탭, 7 비트 계수를 가지는 FIR 필터로 설계하였다. 심볼 타이밍 복구 회로는 Gardner 알고리즘을 이용하여 설계하였으며, 반송파 복구는 결정 지향 알고리즘을 이용하여 설계하였다. 설계된 알고리즘은 VHDL로 코딩되어 FPGA에 구현되었다. 실험에 사용된 FPGA는 ALTERA사의 APEX20KE 시리즈의 60만 게이트 FPGA이다. 구현된 복조기의 성능을 평가하기 위하여 모의실험 결과와 구현 결과를 비교하여 제시하였다. 그 결과로 주파수 오프셋과 위상 오프셋이 있는 경우에도 심볼 타이밍 복구 회로는 잘 동작을 하였으며, 주파수 오프셋이 심볼율의 0.12%까지 위상 동기회로가 잘 동작하였다.

• Journal of Power System Engineering
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• v.6 no.2
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• pp.73-81
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• 2002

In this study, electronically controlled automatic transmission adopted on a subcompact model in the market was modelled, and the driving performances of the transmission were simulated with the models. Kinetic and dynamic models of working components are established. The driving simulation program is developed with those models, and the various driving conditions are analyzed. With the results, the dynamic behaviour of the engine and the automatic transmission is easily understood. Especially, the transient performances of torque converter and clutches are deeply analyzed. Skipping the vehicle road test by using this analyzing tool, we can expect the cost down and the reduction of the development period of automatic transmission.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1092-1099
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• 2001

본 논문에서는 무선 통신 시스템의 중간주파수 처리 단을 디지털로 신호 처리하는 DDC(Digital Down Converter)의 저전력 아키텍처를 제안한다. FIR 필터의 계산량을 줄이기 위해서 개발된 Interpolated FIR 필터가 DDC의 데시메이션 필터로 널리 사용되고 있다. 본 논문은 이와 같은 Interpolated FIR 필터의 개념이 IIR 필터에도 적용될 수 있음을 보이고, 전력 소모와 구현 면적이 기존의 Interpolated FIR 구조보다 더욱 감소된 Interpolated IIR 필터 구조를 제안하였다. CDMA IS-95 DDC 사양의 데시메이션 필터를 FIR 구조, Interpolated FIR 구조, IIR 구조, Interpolated IIR 구조로 구현하여 이 4가지 구조들의 전력소모와 구현 면적을 비교하였으며 제안된 Interpolated IIR 구조가 기존의 Interpolated FIR 구조에 비하여 15.2%의 소모전력 감소와 35.3%의 구현면적의 감소를 달성할 수 있음을 보인다.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.505-511
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• 2008

when electric traction system used DC 1500V runs on decline of rail road track and slows down, dc voltage goes beyond regular voltage. In this case extra power is forcibly wasted by resister because rectifier of substation and electric train including power converter and so on are out of order. This paper described a DC electric railway system, which can generate the excessive DC power form DC bus line to AC source in substation for traction system. The purpose of this study was the development of the regenerative inverter system which suppress extra DC-line voltage and regenerate the energy instead of using a resister. That is Developed regenerative inverter system returns the regenerative energy from the DC line voltage to the utility. In addition, the inverter can be compensate the harmonics caused by the power conversion devices used in the DC traction system.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1984-1987
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• 2002

This paper describes the design and implementation of a single-chip digitally synthesized 0-35MHz agile function generator. The chip comprises an integrated direct digital synthesizer (DDS) with a 10-bit on- chip digital-to-analog converter (DAC) using an n-well single-poly triple-metal 0.5-$\mu\textrm{m}$ CMOS technology. The main features of the chip include maximum clock frequency of 100 MHz at 3.3-V supply voltage, 32-bit frequency tuning word resolution, 12-bit phase tuning word resolution, and an on-chip 10-bit DAC. The chip provides sinusoidal, ramp, saw-tooth, and random waveforms with phase and frequency modulation, and power-down function. At 100-MHz clock frequency, the chip covers a bandwidth from dc to 35 MHz in 0.0233-Hz frequency steps with 190-ns frequency switching speed. The complete chip occupies 12-mm$^2$die area and dissipates 0.4 W at 100-MHz clock frequency.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.75-76
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• 2006

A new broadcasting standard for Digital Multimedia Broadcasting(DMB) has been announced in Korea to provide audio, video, and data broadcasting services. There exist two types of DMB; terrestrial DMB and satellite DMB. And in order to service DMB on the single system, the integration of RF module is required. In this paper, we describe an integrated RF tuner module that can receive T-DMB and S-DMB at the same time, which includes an L-band down-converter, a Band III tuner, and a S-DMB tuner.